From da13511676702180c3abebd18c0217be46c0c95b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 30 Sep 2021 14:55:41 +0100 Subject: [PATCH] remove PartitionedSignal.eq, expectation is to use PartitionedSignal.__Assign__ due to eq being removed, access to the underlying ".sig" is now done using PartitionedSignal.lower() --- src/ieee754/part/partsig.py | 12 ++++++------ src/ieee754/part/test/test_partsig.py | 22 +++++++++++----------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py index 032749cf..a12fb9fe 100644 --- a/src/ieee754/part/partsig.py +++ b/src/ieee754/part/partsig.py @@ -64,8 +64,6 @@ class PartitionedSignal(UserValue): else: self.partpoints = make_partition2(mask, width) - def lower(self): - return self.sig def set_module(self, m): self.m = m @@ -74,9 +72,6 @@ class PartitionedSignal(UserValue): modnames[category] += 1 return "%s_%d" % (category, modnames[category]) - def eq(self, val): - return self.sig.eq(getsig(val)) - @staticmethod def like(other, *args, **kwargs): """Builds a new PartitionedSignal with the same PartitionPoints and @@ -90,6 +85,11 @@ class PartitionedSignal(UserValue): return len(self.sig) def shape(self): return self.sig.shape() + def lower(self): + return self.sig + # now using __Assign__ + #def eq(self, val): + # return self.sig.eq(getsig(val)) # nmigen-redirected constructs (Mux, Cat, Switch, Assign) @@ -100,7 +100,7 @@ class PartitionedSignal(UserValue): "val1 == %d, val2 == %d" % (len(val1), len(val2)) return PMux(self.m, self.partpoints, self, val1, val2) - def __Assign__(self, val): + def __Assign__(self, val, *, src_loc_at=0): # print ("partsig ass", self, val) return PAssign(self.m, self.shape(), val, self.partpoints) diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index fcfa38a8..a862412e 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -106,7 +106,7 @@ class TestAddMod2(Elaboratable): sync += self.mux_out.eq(PMux(m, ppts, self.mux_sel, self.a, self.b)) sync += self.mux_out2.eq(Mux(self.mux_sel2, self.a, self.b)) # scalar left shift - comb += self.bsig.eq(self.b.sig) + comb += self.bsig.eq(self.b.lower()) sync += self.ls_scal_output.eq(self.a << self.bsig) sync += self.rs_scal_output.eq(self.a >> self.bsig) @@ -212,7 +212,7 @@ class TestAddMod(Elaboratable): comb += self.rs_output.eq(self.a >> self.b) ppts = self.partpoints # scalar left shift - comb += self.bsig.eq(self.b.sig) + comb += self.bsig.eq(self.b.lower()) comb += self.ls_scal_output.eq(self.a << self.bsig) # scalar right shift comb += self.rs_scal_output.eq(self.a >> self.bsig) @@ -263,10 +263,10 @@ class TestMux(unittest.TestCase): sel |= maskbit_list[i] selmask |= mask_list[i] - yield module.a.eq(a) - yield module.b.eq(b) + yield module.a.lower().eq(a) + yield module.b.lower().eq(b) yield module.mux_sel.eq(sel) - yield module.mux_sel2.sig.eq(sel) + yield module.mux_sel2.lower().eq(sel) yield Delay(0.1e-6) y = 0 # do the partitioned tests @@ -348,8 +348,8 @@ class TestCat(unittest.TestCase): print ("apart bpart", hex(a), hex(b), list(map(hex, apart)), list(map(hex, bpart))) - yield module.a.eq(a) - yield module.b.eq(b) + yield module.a.lower().eq(a) + yield module.b.lower().eq(b) yield Delay(0.1e-6) y = 0 @@ -528,8 +528,8 @@ class TestPartitionedSignal(unittest.TestCase): (0x0000, 0x0000), (0xFFFF, 0xFFFF), (0x0000, 0xFFFF)] + rand_data: - yield module.a.eq(a) - yield module.b.eq(b) + yield module.a.lower().eq(a) + yield module.b.lower().eq(b) carry_sig = 0xf if carry else 0 yield module.carry_in.eq(carry_sig) yield Delay(0.1e-6) @@ -612,8 +612,8 @@ class TestPartitionedSignal(unittest.TestCase): (0xABCD, 0xABCE), (0x8000, 0x0000), (0xBEEF, 0xFEED)]: - yield module.a.eq(a) - yield module.b.eq(b) + yield module.a.lower().eq(a) + yield module.b.lower().eq(b) yield Delay(0.1e-6) # convert to mask_list mask_list = [] -- 2.30.2