From da1a896b0f95611e506df46e37a8d2b07e1ddd78 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Sat, 8 Jun 2013 12:58:17 -0700 Subject: [PATCH] i965: Emit the BLEND_STATE pointer directly rather than via atoms. Previously, we would: 1. Emit the new indirect state. 2. Flag CACHE_NEW_BLEND_STATE. 3. Rely on later state atoms to notice CACHE_NEW_BLEND_STATE and emit a pointer to the new indirect state. This is rather cumbersome: it requires two state atoms instead of one, and there's a strict ordering dependency in the list. Plus, the code gets spread across two functions (or even files in the case of Gen7+). Gen7+ has a packet to update just the blend state pointer, so it makes a lot of sense to simply emit that right away. Gen6 has a combined packet which updates blending, the color calculator, and depth/stencil state; however, each can still be modified independently. This drops the Gen6 micro-optimization where we tried to only emit one packet that changed all three states. State updates are pretty cheap. CACHE_NEW_BLEND_STATE is no longer necessary, so drop it. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 2 -- src/mesa/drivers/dri/i965/brw_state.h | 1 - src/mesa/drivers/dri/i965/brw_state_upload.c | 2 -- src/mesa/drivers/dri/i965/gen6_cc.c | 23 +++++++++++++++----- src/mesa/drivers/dri/i965/gen7_cc_state.c | 20 ----------------- 5 files changed, 18 insertions(+), 30 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 60b713d37f6..0e3b2abf22d 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -606,7 +606,6 @@ struct brw_vs_prog_data { #define SHADER_TIME_STRIDE 64 enum brw_cache_id { - BRW_BLEND_STATE, BRW_DEPTH_STENCIL_STATE, BRW_COLOR_CALC_STATE, BRW_CC_VP, @@ -701,7 +700,6 @@ enum shader_time_shader_type { /* Flags for brw->state.cache. */ -#define CACHE_NEW_BLEND_STATE (1<intel; struct gl_context *ctx = &brw->intel.ctx; struct gen6_blend_state *blend; int b; @@ -223,7 +224,20 @@ gen6_upload_blend_state(struct brw_context *brw) } } - brw->state.dirty.cache |= CACHE_NEW_BLEND_STATE; + /* Point the GPU at the new indirect state. */ + if (intel->gen == 6) { + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); + OUT_BATCH(brw->cc.blend_state_offset | 1); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); + OUT_BATCH(brw->cc.blend_state_offset | 1); + ADVANCE_BATCH(); + } } const struct brw_tracked_state gen6_blend_state = { @@ -231,7 +245,7 @@ const struct brw_tracked_state gen6_blend_state = { .mesa = (_NEW_COLOR | _NEW_BUFFERS | _NEW_MULTISAMPLE), - .brw = BRW_NEW_BATCH, + .brw = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS, .cache = 0, }, .emit = gen6_upload_blend_state, @@ -279,7 +293,7 @@ static void upload_cc_state_pointers(struct brw_context *brw) BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); - OUT_BATCH(brw->cc.blend_state_offset | 1); + OUT_BATCH(0); OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); OUT_BATCH(brw->cc.state_offset | 1); ADVANCE_BATCH(); @@ -290,8 +304,7 @@ const struct brw_tracked_state gen6_cc_state_pointers = { .mesa = 0, .brw = (BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS), - .cache = (CACHE_NEW_BLEND_STATE | - CACHE_NEW_COLOR_CALC_STATE | + .cache = (CACHE_NEW_COLOR_CALC_STATE | CACHE_NEW_DEPTH_STENCIL_STATE) }, .emit = upload_cc_state_pointers, diff --git a/src/mesa/drivers/dri/i965/gen7_cc_state.c b/src/mesa/drivers/dri/i965/gen7_cc_state.c index b7395aa791b..9ad124e62b3 100644 --- a/src/mesa/drivers/dri/i965/gen7_cc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_cc_state.c @@ -48,26 +48,6 @@ const struct brw_tracked_state gen7_cc_state_pointer = { .emit = upload_cc_state_pointers, }; -static void -upload_blend_state_pointer(struct brw_context *brw) -{ - struct intel_context *intel = &brw->intel; - - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); - OUT_BATCH(brw->cc.blend_state_offset | 1); - ADVANCE_BATCH(); -} - -const struct brw_tracked_state gen7_blend_state_pointer = { - .dirty = { - .mesa = 0, - .brw = BRW_NEW_BATCH, - .cache = CACHE_NEW_BLEND_STATE - }, - .emit = upload_blend_state_pointer, -}; - static void upload_depth_stencil_state_pointer(struct brw_context *brw) { -- 2.30.2