From da2df2fc251440d0dbd91864d74ba94a2153ca5e Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 5 Aug 2009 03:07:55 -0700
Subject: [PATCH] X86: Make conditional moves zero extend their 32 bit
 destinations always.

---
 src/arch/x86/isa/microops/regop.isa | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 6921684a4..dc6819886 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -639,7 +639,7 @@ let {{
 
     class Mov(CondRegOp):
         code = 'DestReg = merge(SrcReg1, op2, dataSize)'
-        else_code = 'DestReg=DestReg;'
+        else_code = 'DestReg = merge(DestReg, DestReg, dataSize);'
 
     # Shift instructions
 
-- 
2.30.2