From da3a99f02db1f53b18aad5a189122ae636e62e48 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 10 Jun 2021 11:52:34 +0100 Subject: [PATCH] moving CLK away from PLL test-out --- 180nm_Oct2020/ls180.mdwn | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn index e0759609f..9ce9a54bd 100644 --- a/180nm_Oct2020/ls180.mdwn +++ b/180nm_Oct2020/ls180.mdwn @@ -17,9 +17,9 @@ auto-generated by [[pinouts.py]] | 24 | N VSSI_7 | | | 25 | N VDDI_7 | | | 27 | N SYS_RST | | -| 28 | N SYS_PLLSELA0 | | -| 29 | N SYS_PLLSELA1 | | -| 30 | N SYS_PLLCLK | | +| 28 | N SYS_PLLCLK | | +| 29 | N SYS_PLLSELA0 | | +| 30 | N SYS_PLLSELA1 | | | 31 | N SYS_PLLTESTOUT | | ## Bank E (32 pins, width 2) @@ -240,9 +240,9 @@ SDRAM System Control -* SYS_PLLCLK : N30/0 -* SYS_PLLSELA0 : N28/0 -* SYS_PLLSELA1 : N29/0 +* SYS_PLLCLK : N28/0 +* SYS_PLLSELA0 : N29/0 +* SYS_PLLSELA1 : N30/0 * SYS_PLLTESTOUT : N31/0 * SYS_PLLVCOUT : E4/0 * SYS_RST : N27/0 @@ -358,9 +358,9 @@ GND * SYS_RST 27 N27/0 -* SYS_PLLSELA0 28 N28/0 -* SYS_PLLSELA1 29 N29/0 -* SYS_PLLCLK 30 N30/0 +* SYS_PLLCLK 28 N28/0 +* SYS_PLLSELA0 29 N29/0 +* SYS_PLLSELA1 30 N30/0 * SYS_PLLTESTOUT 31 N31/0 * SYS_PLLVCOUT 36 E4/0 -- 2.30.2