From da3d55a29c88de69ce7b51151544399e91ef23d8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 27 Feb 2013 17:26:32 +0100 Subject: [PATCH] Added extract -verbose and -map ilang support --- passes/extract/extract.cc | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc index b80d6e889..7541b2603 100644 --- a/passes/extract/extract.cc +++ b/passes/extract/extract.cc @@ -185,6 +185,7 @@ struct ExtractPass : public Pass { log_push(); std::string filename; + bool verbose; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -192,21 +193,33 @@ struct ExtractPass : public Pass { filename = args[++argidx]; continue; } + if (args[argidx] == "-verbose") { + verbose = true; + continue; + } break; } extra_args(args, argidx, design); if (filename.empty()) - log_cmd_error("Missing option -map .\n"); + log_cmd_error("Missing option -map .\n"); RTLIL::Design *map = new RTLIL::Design; FILE *f = fopen(filename.c_str(), "rt"); if (f == NULL) log_error("Can't open map file `%s'\n", filename.c_str()); - Frontend::frontend_call(map, f, filename, "verilog"); + if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") + Frontend::frontend_call(map, f, filename, "ilang"); + else + Frontend::frontend_call(map, f, filename, "verilog"); fclose(f); SubCircuit::Solver solver; + std::vector results; + + if (verbose) + solver.setVerbose(); + std::map needle_map, haystack_map; log_header("Creating graphs for SubCircuit library.\n"); @@ -233,9 +246,6 @@ struct ExtractPass : public Pass { log_header("Running solver from SubCircuit library.\n"); - solver.setVerbose(); - std::vector results; - for (auto &needle_it : needle_map) for (auto &haystack_it : haystack_map) { log("Solving for %s in %s.\n", needle_it.first.c_str(), haystack_it.first.c_str()); -- 2.30.2