From da7853cc18318966aafa5a3cf48aedc4e671404d Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Tue, 26 Sep 2017 10:32:58 +0000 Subject: [PATCH] S/390: Add widening vector mult lo/hi patterns Add support for widening vector multiply lo/hi patterns. These do not directly match on IBM Z instructions but can be emulated with even/odd + vector merge. gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vector.md ("vec_widen_umult_lo_") ("vec_widen_umult_hi_", "vec_widen_smult_lo_") ("vec_widen_smult_hi_"): New expander definitions. From-SVN: r253192 --- gcc/ChangeLog | 6 +++ gcc/config/s390/vector.md | 83 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 85 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5e7f82dc2c4..9df1ff54470 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-09-26 Andreas Krebbel + + * config/s390/vector.md ("vec_widen_umult_lo_") + ("vec_widen_umult_hi_", "vec_widen_smult_lo_") + ("vec_widen_smult_hi_"): New expander definitions. + 2017-09-26 Richard Earnshaw PR target/82175 diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 3cf79896720..29131cdbf35 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1065,10 +1065,85 @@ "vmlo\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) -; vec_widen_umult_hi -; vec_widen_umult_lo -; vec_widen_smult_hi -; vec_widen_smult_lo + +; Widening hi/lo multiplications + +; The S/390 instructions vml and vmh return the low or high parts of +; the double sized result elements in the corresponding elements of +; the target register. That's NOT what the vec_widen_umult_lo/hi +; patterns are expected to do. + +; We emulate the widening lo/hi multiplies with the even/odd versions +; followed by a vector merge + + +(define_expand "vec_widen_umult_lo_" + [(set (match_dup 3) + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (match_operand:VI_QHS 2 "register_operand" "v")] + UNSPEC_VEC_UMULT_EVEN)) + (set (match_dup 4) + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_UMULT_ODD)) + (set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_dup 3) (match_dup 4)] + UNSPEC_VEC_MERGEL))] + "TARGET_VX" + { + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); + }) + +(define_expand "vec_widen_umult_hi_" + [(set (match_dup 3) + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (match_operand:VI_QHS 2 "register_operand" "v")] + UNSPEC_VEC_UMULT_EVEN)) + (set (match_dup 4) + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_UMULT_ODD)) + (set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_dup 3) (match_dup 4)] + UNSPEC_VEC_MERGEH))] + "TARGET_VX" + { + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); + }) + +(define_expand "vec_widen_smult_lo_" + [(set (match_dup 3) + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (match_operand:VI_QHS 2 "register_operand" "v")] + UNSPEC_VEC_SMULT_EVEN)) + (set (match_dup 4) + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_SMULT_ODD)) + (set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_dup 3) (match_dup 4)] + UNSPEC_VEC_MERGEL))] + "TARGET_VX" + { + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); + }) + +(define_expand "vec_widen_smult_hi_" + [(set (match_dup 3) + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (match_operand:VI_QHS 2 "register_operand" "v")] + UNSPEC_VEC_SMULT_EVEN)) + (set (match_dup 4) + (unspec: [(match_dup 1) (match_dup 2)] + UNSPEC_VEC_SMULT_ODD)) + (set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_dup 3) (match_dup 4)] + UNSPEC_VEC_MERGEH))] + "TARGET_VX" + { + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); + }) ; vec_widen_ushiftl_hi ; vec_widen_ushiftl_lo -- 2.30.2