From da86c81e6522f9b27cffd04f728e0edd937d09fc Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Fri, 9 Feb 2018 10:32:37 -0600 Subject: [PATCH] re PR target/83926 (ICE during RTL pass: ira, in elimination_costs_in_insn, at reload1.c:3633) gcc/ PR target/83926 * config/rs6000/vsx.md (vsx_mul_v2di): Handle generating a 64-bit multiply in 32-bit mode. (vsx_div_v2di): Handle generating a 64-bit signed divide in 32-bit mode. (vsx_udiv_v2di): Handle generating a 64-bit unsigned divide in 32-bit mode. gcc/testsuite/ PR target/83926 * gcc.target/powerpc/pr83926.c: New test. * gcc.target/powerpc/builtins-1-be.c: Filter out gimple folding disabled message. Fix test for running in 32-bit mode. From-SVN: r257531 --- gcc/ChangeLog | 9 +++ gcc/config/rs6000/vsx.md | 64 +++++++++++++++-- gcc/testsuite/ChangeLog | 7 ++ .../gcc.target/powerpc/builtins-1-be.c | 68 ++++++++++--------- gcc/testsuite/gcc.target/powerpc/pr83926.c | 22 ++++++ 5 files changed, 133 insertions(+), 37 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr83926.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 02a7ea064a8..c42ffa648bc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2018-02-09 Peter Bergner + + PR target/83926 + * config/rs6000/vsx.md (vsx_mul_v2di): Handle generating a 64-bit + multiply in 32-bit mode. + (vsx_div_v2di): Handle generating a 64-bit signed divide in 32-bit mode. + (vsx_udiv_v2di): Handle generating a 64-bit unsigned divide in 32-bit + mode. + 2018-02-09 Sebastian Perta * config/rx/constraints.md: added new constraint CALL_OP_SYMBOL_REF diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c2016f1bf71..86efdced2a8 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1650,10 +1650,22 @@ rtx op5 = gen_reg_rtx (DImode); emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); - emit_insn (gen_muldi3 (op5, op3, op4)); + if (TARGET_POWERPC64) + emit_insn (gen_muldi3 (op5, op3, op4)); + else + { + rtx ret = expand_mult (DImode, op3, op4, NULL, 0, false); + emit_move_insn (op5, ret); + } emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); - emit_insn (gen_muldi3 (op3, op3, op4)); + if (TARGET_POWERPC64) + emit_insn (gen_muldi3 (op3, op3, op4)); + else + { + rtx ret = expand_mult (DImode, op3, op4, NULL, 0, false); + emit_move_insn (op3, ret); + } emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; }" @@ -1688,10 +1700,30 @@ rtx op5 = gen_reg_rtx (DImode); emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); - emit_insn (gen_divdi3 (op5, op3, op4)); + if (TARGET_POWERPC64) + emit_insn (gen_divdi3 (op5, op3, op4)); + else + { + rtx libfunc = optab_libfunc (sdiv_optab, DImode); + rtx target = emit_library_call_value (libfunc, + op5, LCT_NORMAL, DImode, + op3, DImode, + op4, DImode); + emit_move_insn (op5, target); + } emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); - emit_insn (gen_divdi3 (op3, op3, op4)); + if (TARGET_POWERPC64) + emit_insn (gen_divdi3 (op3, op3, op4)); + else + { + rtx libfunc = optab_libfunc (sdiv_optab, DImode); + rtx target = emit_library_call_value (libfunc, + op3, LCT_NORMAL, DImode, + op3, DImode, + op4, DImode); + emit_move_insn (op3, target); + } emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; }" @@ -1716,10 +1748,30 @@ rtx op5 = gen_reg_rtx (DImode); emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); - emit_insn (gen_udivdi3 (op5, op3, op4)); + if (TARGET_POWERPC64) + emit_insn (gen_udivdi3 (op5, op3, op4)); + else + { + rtx libfunc = optab_libfunc (udiv_optab, DImode); + rtx target = emit_library_call_value (libfunc, + op5, LCT_NORMAL, DImode, + op3, DImode, + op4, DImode); + emit_move_insn (op5, target); + } emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); - emit_insn (gen_udivdi3 (op3, op3, op4)); + if (TARGET_POWERPC64) + emit_insn (gen_udivdi3 (op3, op3, op4)); + else + { + rtx libfunc = optab_libfunc (udiv_optab, DImode); + rtx target = emit_library_call_value (libfunc, + op3, LCT_NORMAL, DImode, + op3, DImode, + op4, DImode); + emit_move_insn (op3, target); + } emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; }" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 24751af6d36..f381e22a9b9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2018-02-09 Peter Bergner + + PR target/83926 + * gcc.target/powerpc/pr83926.c: New test. + * gcc.target/powerpc/builtins-1-be.c: Filter out gimple folding disabled + message. Fix test for running in 32-bit mode. + 2018-02-09 Tamar Christina PR target/82641 diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c index aaaf79dad04..fb807665535 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc64-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple" } */ +/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */ +/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */ /* Test that a number of newly added builtin overloads are accepted by the compiler. */ @@ -22,10 +23,10 @@ vec_ctf xvmuldp vec_cts xvcvdpsxds, vctsxs vec_ctu xvcvdpuxds, vctuxs - vec_div divd, divdu + vec_div divd, divdu | __divdi3(), __udivdi3() vec_mergel vmrghb, vmrghh, xxmrghw vec_mergeh xxmrglw, vmrglh - vec_mul mulld + vec_mul mulld | mullw, mulhwu vec_nor xxlnor vec_or xxlor vec_packsu vpksdus @@ -36,34 +37,39 @@ vec_rsqrt xvrsqrtesp vec_rsqrte xvrsqrtesp */ -/* { dg-final { scan-assembler-times "vcmpequd." 4 } } */ -/* { dg-final { scan-assembler-times "vcmpgtud." 8 } } */ -/* { dg-final { scan-assembler-times "xxland" 29 } } */ -/* { dg-final { scan-assembler-times "vclzb" 2 } } */ -/* { dg-final { scan-assembler-times "vclzb" 2 } } */ -/* { dg-final { scan-assembler-times "vclzw" 2 } } */ -/* { dg-final { scan-assembler-times "vclzh" 2 } } */ -/* { dg-final { scan-assembler-times "xvcpsgnsp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 6 } } */ -/* { dg-final { scan-assembler-times "xvcvdpsxds" 1 } } */ -/* { dg-final { scan-assembler-times "vctsxs" 1 } } */ -/* { dg-final { scan-assembler-times "xvcvdpuxds" 1 } } */ -/* { dg-final { scan-assembler-times "vctuxs" 1 } } */ -/* { dg-final { scan-assembler-times "divd" 4 } } */ -/* { dg-final { scan-assembler-times "divdu" 2 } } */ -/* { dg-final { scan-assembler-times "vmrghb" 0 } } */ -/* { dg-final { scan-assembler-times "vmrghh" 3 } } */ -/* { dg-final { scan-assembler-times "xxmrghw" 1 } } */ -/* { dg-final { scan-assembler-times "xxmrglw" 4 } } */ -/* { dg-final { scan-assembler-times "vmrglh" 4 } } */ -/* { dg-final { scan-assembler-times "mulld" 4 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 19 } } */ -/* { dg-final { scan-assembler-times "xxlor" 14 } } */ -/* { dg-final { scan-assembler-times "vpksdus" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 1 } } */ -/* { dg-final { scan-assembler-times "xxsel" 6 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 6 } } */ +/* { dg-final { scan-assembler-times {\mvcmpequd\M\.} 4 } } */ +/* { dg-final { scan-assembler-times {\mvcmpgtud\M\.} 8 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 16 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvclzb\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvclzb\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvclzw\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvclzh\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvcpsgnsp\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvmuldp\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxvcvdpsxds\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvctsxs\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvcvdpuxds\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvctuxs\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmrghb\M} 0 } } */ +/* { dg-final { scan-assembler-times {\mvmrghh\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxmrghw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxxmrglw\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mvmrglh\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 6 } } */ +/* { dg-final { scan-assembler-times {(?n)\mxxlor\M.*\mboolv4si3_internal\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mvpksdus\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvperm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxxsel\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mbl __divdi3\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mbl __udivdi3\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mmullw\M} 12 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mmulhwu\M} 4 { target ilp32 } } } */ /* The source code for the test is in builtins-1.h. */ #include "builtins-1.h" diff --git a/gcc/testsuite/gcc.target/powerpc/pr83926.c b/gcc/testsuite/gcc.target/powerpc/pr83926.c new file mode 100644 index 00000000000..3188ade6f0b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr83926.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-O2 -mcpu=power8 -mno-fold-gimple" } */ + +__attribute__ ((altivec(vector__))) long long +sdiv (__attribute__ ((altivec(vector__))) long long a, + __attribute__ ((altivec(vector__))) long long b) +{ + return __builtin_vsx_div_2di (a, b); +} +__attribute__ ((altivec(vector__))) unsigned long long +udiv (__attribute__ ((altivec(vector__))) unsigned long long a, + __attribute__ ((altivec(vector__))) unsigned long long b) +{ + return __builtin_vsx_udiv_2di (a, b); +} +__attribute__ ((altivec(vector__))) long long +smul (__attribute__ ((altivec(vector__))) long long a, + __attribute__ ((altivec(vector__))) long long b) +{ + return __builtin_vsx_mul_2di (a, b); +} -- 2.30.2