From da9155685471591d5e53da30405b7f58c418b7d3 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 4 Apr 2023 05:19:57 +0100 Subject: [PATCH] Power ISA tech ref is dual column only 3.5in per column @ 9pt. also not clear. --- openpower/sv/rfc/ls006.mdwn | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn index e7c616ec9..338e156b8 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.mdwn @@ -320,12 +320,16 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | | Assembly Alias | Full Instruction | -|----------------------|----------------------|------|----------------------|----------------------| -| `fcvtfgw FRT, RB` | `fcvtfg FRT, RB, 0` | | `fcvtfgd FRT, RB` | `fcvtfg FRT, RB, 2` | -| `fcvtfgw. FRT, RB` | `fcvtfg. FRT, RB, 0` | | `fcvtfgd. FRT, RB` | `fcvtfg. FRT, RB, 2` | -| `fcvtfguw FRT, RB` | `fcvtfg FRT, RB, 1` | | `fcvtfgud FRT, RB` | `fcvtfg FRT, RB, 3` | -| `fcvtfguw. FRT, RB` | `fcvtfg. FRT, RB, 1` | | `fcvtfgud. FRT, RB` | `fcvtfg. FRT, RB, 3` | +| Assembly Alias | Full Instruction | +|----------------------|----------------------| +| `fcvtfgw FRT, RB` | `fcvtfg FRT, RB, 0` | +| `fcvtfgw. FRT, RB` | `fcvtfg. FRT, RB, 0` | +| `fcvtfguw FRT, RB` | `fcvtfg FRT, RB, 1` | +| `fcvtfguw. FRT, RB` | `fcvtfg. FRT, RB, 1` | +| `fcvtfgd FRT, RB` | `fcvtfg FRT, RB, 2` | +| `fcvtfgd. FRT, RB` | `fcvtfg. FRT, RB, 2` | +| `fcvtfgud FRT, RB` | `fcvtfg FRT, RB, 3` | +| `fcvtfgud. FRT, RB` | `fcvtfg. FRT, RB, 3` | ---------- @@ -385,12 +389,16 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | | Assembly Alias | Full Instruction | -|----------------------|----------------------|------|----------------------|----------------------| -| `fcvtfgws FRT, RB` | `fcvtfg FRT, RB, 0` | | `fcvtfgds FRT, RB` | `fcvtfg FRT, RB, 2` | -| `fcvtfgws. FRT, RB` | `fcvtfg. FRT, RB, 0` | | `fcvtfgds. FRT, RB` | `fcvtfg. FRT, RB, 2` | -| `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1` | | `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3` | -| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` | | `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` | +| Assembly Alias | Full Instruction | +|----------------------|----------------------| +| `fcvtfgws FRT, RB` | `fcvtfg FRT, RB, 0` | +| `fcvtfgws. FRT, RB` | `fcvtfg. FRT, RB, 0` | +| `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1` | +| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` | +| `fcvtfgds FRT, RB` | `fcvtfg FRT, RB, 2` | +| `fcvtfgds. FRT, RB` | `fcvtfg. FRT, RB, 2` | +| `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3` | +| `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` | ---------- -- 2.30.2