From dac71983e1118fc7f524a7006884a43498c4cdbb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 17:33:24 +0100 Subject: [PATCH] add category descriptions --- simple_v_extension/opcodes.mdwn | 3 +++ 1 file changed, 3 insertions(+) diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index 1bcf29253..efe05fbcf 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -6,6 +6,9 @@ page categorises and identifies the type of parallelism that SimpleV indirectly adds on each RISC-V **standard** opcode. These are note-form: see [[specification]] for full details. +Note that the list is necessarily incomplete, as any custom or future +extensions may also benefit from fitting one of the categories below. + * **-** no change of behaviour takes place: operation remains **completely scalar** as an **unmodified**, unaugmented standard RISC-V opcode, even if it has registers. -- 2.30.2