From daccb4b35c49464bb103fe18e33380eaba7206a7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 May 2019 23:53:53 +0100 Subject: [PATCH] got working (sort-of) cscore6600 --- src/experiment/cscore.py | 33 +++++++++++++++---------------- src/experiment/score6600.py | 23 +++++++++++++-------- src/scoreboard/dependence_cell.py | 2 +- src/scoreboard/fn_unit.py | 2 +- src/scoreboard/fu_dep_cell.py | 5 +++-- src/scoreboard/fu_fu_matrix.py | 10 +++++----- 6 files changed, 41 insertions(+), 34 deletions(-) diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index cbc76f99..ff66b91e 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -164,11 +164,11 @@ class Scoreboard(Elaboratable): # XXX sync, again to avoid an infinite loop. is it the right thing??? # Group Picker... done manually for now. TODO: cat array of pick sigs - m.d.sync += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd - m.d.sync += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr + m.d.comb += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd + m.d.comb += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr - m.d.sync += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd - m.d.sync += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr + m.d.comb += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd + m.d.comb += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr # create read-pending FU-FU vectors intfu_rd_pend_v = Signal(n_int_fus, reset_less = True) @@ -188,17 +188,17 @@ class Scoreboard(Elaboratable): # to be unit "read-pending / write-pending" m.d.comb += intfudeps.rd_pend_i.eq(intfu_rd_pend_v) m.d.comb += intfudeps.wr_pend_i.eq(intfu_wr_pend_v) - m.d.sync += intfudeps.issue_i.eq(issueunit.i.fn_issue_o) + m.d.comb += intfudeps.issue_i.eq(issueunit.i.fn_issue_o) for i in range(n_int_fus): - m.d.sync += intfudeps.go_rd_i[i].eq(intpick1.go_rd_o[i]) - m.d.sync += intfudeps.go_wr_i[i].eq(intpick1.go_wr_o[i]) + m.d.comb += intfudeps.go_rd_i[i].eq(intpick1.go_rd_o[i]) + m.d.comb += intfudeps.go_wr_i[i].eq(intpick1.go_wr_o[i]) # Connect Picker (note connection to FU-FU) #--------- readable_o = intfudeps.readable_o writable_o = intfudeps.writable_o - m.d.comb += intpick1.rd_rel_i[0].eq(fn_busy_l[0]) - m.d.comb += intpick1.rd_rel_i[1].eq(fn_busy_l[1]) + m.d.comb += intpick1.rd_rel_i[0].eq(int_alus[0].rd_rel_o) + m.d.comb += intpick1.rd_rel_i[1].eq(int_alus[1].rd_rel_o) m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o) m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o) m.d.comb += intpick1.readable_i[0].eq(readable_o[0]) # add rd @@ -209,22 +209,22 @@ class Scoreboard(Elaboratable): #--------- # Connect Register File(s) #--------- - with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i): - m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o) + #with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i): + m.d.sync += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o) #with m.If(intpick1.go_rd_o): #with m.If(if_l[0].go_rd_i | if_l[1].go_rd_i): - m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o) - m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o) + m.d.sync += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o) + m.d.sync += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o) # merge (OR) all integer FU / ALU outputs to a single value # bit of a hack: treereduce needs a list with an item named "dest_o" dest_o = treereduce(int_alus) - m.d.comb += int_dest.data_i.eq(dest_o) + m.d.sync += int_dest.data_i.eq(dest_o) # connect ALUs for i, alu in enumerate(int_alus): - m.d.sync += alu.go_rd_i.eq(intpick1.go_rd_o[i]) - m.d.sync += alu.go_wr_i.eq(intpick1.go_wr_o[i]) + m.d.comb += alu.go_rd_i.eq(intpick1.go_rd_o[i]) + m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i]) m.d.comb += alu.issue_i.eq(fn_issue_l[i]) #m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue m.d.comb += alu.src1_i.eq(int_src1.data_o) @@ -387,7 +387,6 @@ def scoreboard_sim(dut, alusim): yield yield yield - yield yield diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index daec9029..cab033be 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -96,13 +96,14 @@ class FunctionUnits(Elaboratable): self.src1_i = Signal(n_regs, reset_less=True) # oper1 R# in self.src2_i = Signal(n_regs, reset_less=True) # oper2 R# in + self.g_int_rd_pend_o = Signal(n_regs, reset_less=True) + self.g_int_wr_pend_o = Signal(n_regs, reset_less=True) + self.dest_rsel_o = Signal(n_regs, reset_less=True) # dest reg (bot) self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot) self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot) self.req_rel_i = Signal(n_int_alus, reset_less = True) - self.g_int_rd_pend_o = Signal(n_regs, reset_less=True) - self.g_int_wr_pend_o = Signal(n_regs, reset_less=True) self.readable_o = Signal(n_int_alus, reset_less=True) self.writable_o = Signal(n_int_alus, reset_less=True) @@ -123,11 +124,14 @@ class FunctionUnits(Elaboratable): intregdeps = FURegDepMatrix(n_int_fus, self.n_regs) m.submodules.intregdeps = intregdeps - m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_pend_o) - m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_pend_o) + m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o) + m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o) - m.d.comb += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o) - m.d.comb += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o) + m.d.comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o) + m.d.comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o) + + m.d.comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o) + m.d.comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o) m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i) m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i) @@ -392,8 +396,8 @@ def scoreboard_sim(dut, alusim): instrs.append((5, 3, 3, 1)) if True: - instrs.append((1, 1, 2, 1)) - instrs.append((1, 2, 2, 0)) + instrs.append((5, 6, 2, 1)) + instrs.append((2, 2, 4, 0)) #instrs.append((2, 2, 3, 1)) for i, (src1, src2, dest, op) in enumerate(instrs): @@ -412,6 +416,9 @@ def scoreboard_sim(dut, alusim): yield from print_reg(dut, [1,2,3]) yield yield from print_reg(dut, [1,2,3]) + yield + yield + yield yield yield from print_reg(dut, [1,2,3]) diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 9a54e3a4..9cab03bf 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -51,7 +51,7 @@ class DepCell(Elaboratable): m.d.comb += l.r.eq(self.go_i) # Function Unit "Forward Progress". - m.d.comb += self.fwd_o.eq((cq | l.q) & self.hazard_i & ~self.issue_i) + m.d.comb += self.fwd_o.eq((cq | l.q) & self.hazard_i)# & ~self.issue_i) # Register Select. Activated on go read/write and *current* latch set m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i) diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py index 3edabbde..886c8cf2 100644 --- a/src/scoreboard/fn_unit.py +++ b/src/scoreboard/fn_unit.py @@ -165,7 +165,7 @@ class FnUnit(Elaboratable): ro = Signal(reset_less=True) m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o) m.d.comb += ro.eq(~g_rd.bool()) - m.d.comb += self.readable_o.eq(ro & rd_l.q) + m.d.comb += self.readable_o.eq(ro) # writable output signal g_wr_v = Signal(self.reg_width, reset_less=True) diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py index a2f142b7..544c3265 100644 --- a/src/scoreboard/fu_dep_cell.py +++ b/src/scoreboard/fu_dep_cell.py @@ -3,6 +3,7 @@ from nmigen.cli import verilog, rtlil from nmigen import Module, Signal, Elaboratable from nmutil.latch import SRLatch + class DepCell(Elaboratable): """ FU Dependency Cell """ @@ -72,8 +73,8 @@ class FUDependenceCell(Elaboratable): m.d.comb += rd_c.go_i.eq(self.go_rd_i) # connect pend_i - m.d.comb += wr_c.go_i.eq(self.wr_pend_i) - m.d.comb += rd_c.go_i.eq(self.rd_pend_i) + m.d.comb += wr_c.pend_i.eq(self.wr_pend_i) + m.d.comb += rd_c.pend_i.eq(self.rd_pend_i) # connect output m.d.comb += self.wr_wait_o.eq(wr_c.wait_o) diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py index bb7f8b18..1f868081 100644 --- a/src/scoreboard/fu_fu_matrix.py +++ b/src/scoreboard/fu_fu_matrix.py @@ -81,11 +81,11 @@ class FUFUDepMatrix(Elaboratable): fu.wr_pend_i.eq(Cat(*wr_wait_o)), ] # --- - # connect Dependency Matrix issue to module issue + # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i # --- - for y in range(self.n_fu_row): + for x in range(self.n_fu_col): issue_i = [] - for x in range(self.n_fu_col): + for y in range(self.n_fu_row): dc = dm[x][y] # accumulate cell inputs issue issue_i.append(dc.issue_i) @@ -111,10 +111,10 @@ class FUFUDepMatrix(Elaboratable): # --- # connect Matrix pending # --- - for x in range(self.n_fu_col): + for y in range(self.n_fu_row): rd_pend_i = [] wr_pend_i = [] - for y in range(self.n_fu_row): + for x in range(self.n_fu_col): dc = dm[x][y] # accumulate cell rd_pend/wr_pend/go_rd/go_wr rd_pend_i.append(dc.rd_pend_i) -- 2.30.2