From dad91206531d7e3ad48cf5c6ff9ce978a622f19c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 11 Dec 2011 20:16:50 +0100 Subject: [PATCH] bus: 14-bit CSR addresses --- migen/bus/csr.py | 2 +- migen/bus/wishbone2csr.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 297bd4e4..667d58b8 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -2,7 +2,7 @@ from migen.fhdl import structure as f from .simple import Simple _desc = [ - (True, "a", 16), + (True, "a", 14), (True, "we", 1), (True, "d", 32), (False, "d", 32) diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py index 6d009904..9c0a4c24 100644 --- a/migen/bus/wishbone2csr.py +++ b/migen/bus/wishbone2csr.py @@ -14,7 +14,7 @@ class Inst(): sync = [ f.Assign(self.csr.we_o, self.wishbone.we_i), f.Assign(self.csr.d_o, self.wishbone.dat_i), - f.Assign(self.csr.a_o, self.wishbone.adr_i[:16]), + f.Assign(self.csr.a_o, self.wishbone.adr_i[2:16]), f.Assign(self.wishbone.ack_o, 0), f.Assign(self.wishbone.dat_o, self.csr.d_i) ] -- 2.30.2