From db4237a4cb3744c130f307431ed6bb9cafa05f7f Mon Sep 17 00:00:00 2001
From: Jeffrey A Law <law@cygnus.com>
Date: Wed, 24 Mar 1999 00:30:32 +0000
Subject: [PATCH] pa.md (rotlsi3): New expander.

        * pa.md (rotlsi3): New expander.  Synthesize a variable rotate
        left using a variable rotate right.  Provide anonymous pattern for
        rotate left by a constant value.

From-SVN: r25936
---
 gcc/ChangeLog       |  4 ++++
 gcc/config/pa/pa.md | 30 ++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9573ce784c4..def552bbeeb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 Tue Mar 23 23:32:14 1999  Jeffrey A Law  (law@cygnus.com)
 
+	* pa.md (rotlsi3): New expander.  Synthesize a variable rotate
+	left using a variable rotate right.  Provide anonymous pattern for
+	rotate left by a constant value.
+
 	* expr.c (expand_assignment): Do not try to optimize a aggregate
 	address which has VOIDmode.
 
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 0edbf3139cd..078a04efd68 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3901,6 +3901,36 @@
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
+(define_expand "rotlsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+        (rotate:SI (match_operand:SI 1 "register_operand" "")
+                   (match_operand:SI 2 "arith32_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT)
+    {
+      rtx temp = gen_reg_rtx (SImode);
+      emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
+      emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
+      DONE;
+    }
+  /* Else expand normally.  */
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (rotate:SI (match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "const_int_operand" "n")))]
+  ""
+  "*
+{
+  operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
+  return \"shd %1,%1,%2,%0\";
+}"
+  [(set_attr "type" "shift")
+   (set_attr "length" "4")])
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operator:SI 5 "plus_xor_ior_operator"
-- 
2.30.2