From db7914a096aa7028b01ea6fdd71e53beea62f680 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 May 2020 18:16:28 +0100 Subject: [PATCH] debug info on assertion --- src/soc/logical/test/test_pipe_caller.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py index f93cffd5..58c331fb 100644 --- a/src/soc/logical/test/test_pipe_caller.py +++ b/src/soc/logical/test/test_pipe_caller.py @@ -187,7 +187,7 @@ class TestRunner(FHDLTestCase): yield instruction.eq(ins) # raw binary instr. yield Settle() fn_unit = yield pdecode2.e.fn_unit - self.assertEqual(fn_unit, Function.LOGICAL.value) + self.assertEqual(fn_unit, Function.LOGICAL.value, code) yield from set_alu_inputs(alu, pdecode2, simulator) yield from set_extra_alu_inputs(alu, pdecode2, simulator) yield @@ -206,7 +206,7 @@ class TestRunner(FHDLTestCase): write_reg_idx = yield pdecode2.e.write_reg.data expected = simulator.gpr(write_reg_idx).value print(f"expected {expected:x}, actual: {alu_out:x}") - self.assertEqual(expected, alu_out) + self.assertEqual(expected, alu_out, code) yield from self.check_extra_alu_outputs(alu, pdecode2, simulator) -- 2.30.2