From db7a48c05dec0f2e737dc9ee6726da20d70db514 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Jan 2020 13:24:06 +0100 Subject: [PATCH] soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL --- litex/soc/cores/clock.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 03b7e426..252cd491 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -448,7 +448,7 @@ class iCE40PLL(Module): valid = False for divq in range(*self.divq_range): clk_freq = vco_freq/(2**divq) - if abs(clk_freq - f) < f*m: + if abs(clk_freq - f) <= f*m: config["divq"] = divq valid = True break @@ -541,7 +541,7 @@ class ECP5PLL(Module): valid = False for d in range(*self.clko_div_range): clk_freq = vco_freq/d - if abs(clk_freq - f) < f*m: + if abs(clk_freq - f) <= f*m: config["clko{}_freq".format(n)] = clk_freq config["clko{}_div".format(n)] = d config["clko{}_phase".format(n)] = p -- 2.30.2