From db818fbb322dfd1b0246ba2873696a7eedf6acad Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 13 Aug 2022 11:29:11 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index cfbe04b1e..c85d349d3 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -232,3 +232,21 @@ element result is *always* discarded, never written (just like `cmp`). Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd. +# Pack/Unpack Mode + +Structured Pack/Unpack is similar to VSX `vpack` and `vunpack` except +generalised not only to a Schedule to be applied to any operation but +also extended to vec2/3/4. + +Setting this mode changes the meaning of bits 4-5 in `RM` from being +`ELWIDTH` to a pair of Pack/Unpack bits. Thus it is not possible +to separately override source and destination elwidths at the same +time as use Pack/Unpack: the `SRC_ELWIDTH` bits (6-7) must be used as +both source and destination elwidth. + +This was considered to be an acceptable +compromise. If separate elwidths are required and Pack/Unpack +needed without needing to perform a widening or narrowing register +move then [[sv/remap]] may be used: Matrix Mode may perform the +same operation (but is more costly to set up). + -- 2.30.2