From dbae576f7f25fef72ca0b9f6f4822e0fddf7d607 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Fri, 19 Jun 2015 13:36:15 -0700 Subject: [PATCH] i965: add EXT_polygon_offset_clamp support to gen4/gen5 Reviewed-by: Matt Turner Signed-off-by: Ilia Mirkin --- src/mesa/drivers/dri/i965/brw_clip.c | 1 + src/mesa/drivers/dri/i965/brw_clip.h | 1 + src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 14 ++++++++++++++ src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_misc_state.c | 8 -------- src/mesa/drivers/dri/i965/brw_wm_state.c | 11 +++++++++++ src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 7 files changed, 30 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index 3a73c64a88b..2d5abc70cb9 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -223,6 +223,7 @@ brw_upload_clip_prog(struct brw_context *brw) /* _NEW_POLYGON, _NEW_BUFFERS */ key.offset_units = ctx->Polygon.OffsetUnits * ctx->DrawBuffer->_MRD * 2; key.offset_factor = ctx->Polygon.OffsetFactor * ctx->DrawBuffer->_MRD; + key.offset_clamp = ctx->Polygon.OffsetClamp * ctx->DrawBuffer->_MRD; } if (!ctx->Polygon._FrontBit) { diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index 4e38f2f2ed6..54c76822e22 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -62,6 +62,7 @@ struct brw_clip_prog_key { GLfloat offset_factor; GLfloat offset_units; + GLfloat offset_clamp; }; diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c index 6baf620a1a7..9a4d2a9d6f9 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c @@ -188,6 +188,12 @@ static void copy_bfc( struct brw_clip_compile *c ) GLfloat bc = dir.y * iz; offset = ctx->Polygon.OffsetUnits * DEPTH_SCALE; offset += MAX2( abs(ac), abs(bc) ) * ctx->Polygon.OffsetFactor; + if (ctx->Polygon.OffsetClamp && isfinite(ctx->Polygon.OffsetClamp)) { + if (ctx->Polygon.OffsetClamp < 0) + offset = MAX2( offset, ctx->Polygon.OffsetClamp ); + else + offset = MIN2( offset, ctx->Polygon.OffsetClamp ); + } offset *= MRD; */ static void compute_offset( struct brw_clip_compile *c ) @@ -211,6 +217,14 @@ static void compute_offset( struct brw_clip_compile *c ) brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor)); brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units)); + if (c->key.offset_clamp && isfinite(c->key.offset_clamp)) { + brw_CMP(p, + vec1(brw_null_reg()), + c->key.offset_clamp < 0 ? BRW_CONDITIONAL_GE : BRW_CONDITIONAL_L, + vec1(off), + brw_imm_f(c->key.offset_clamp)); + brw_SEL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_clamp)); + } } diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 546f8fc35fe..0a29a692016 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1457,6 +1457,8 @@ struct brw_context */ drm_intel_bo *multisampled_null_render_target_bo; uint32_t fast_clear_op; + + float offset_clamp; } wm; struct { diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 7d17edb9023..cf6ba5b4aeb 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -887,14 +887,6 @@ brw_upload_invariant_state(struct brw_context *brw) brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); brw->last_pipeline = BRW_RENDER_PIPELINE; - if (brw->gen < 6) { - /* Disable depth offset clamping. */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); - OUT_BATCH_F(0.0); - ADVANCE_BATCH(); - } - if (brw->gen >= 8) { BEGIN_BATCH(3); OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2)); diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index cd0b56ba60c..ec54ef2acd9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -31,6 +31,7 @@ +#include "intel_batchbuffer.h" #include "intel_fbo.h" #include "brw_context.h" #include "brw_state.h" @@ -251,6 +252,16 @@ brw_upload_wm_unit(struct brw_context *brw) } brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; + + /* _NEW_POLGYON */ + if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) { + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); + OUT_BATCH_F(ctx->Polygon.OffsetClamp); + ADVANCE_BATCH(); + + brw->wm.offset_clamp = ctx->Polygon.OffsetClamp; + } } const struct brw_tracked_state brw_wm_unit = { diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 3c77f4773c6..3f9afd16c71 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -229,6 +229,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.EXT_packed_float = true; ctx->Extensions.EXT_pixel_buffer_object = true; ctx->Extensions.EXT_point_parameters = true; + ctx->Extensions.EXT_polygon_offset_clamp = true; ctx->Extensions.EXT_provoking_vertex = true; ctx->Extensions.EXT_stencil_two_side = true; ctx->Extensions.EXT_texture_array = true; @@ -300,7 +301,6 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.AMD_vertex_shader_layer = true; ctx->Extensions.EXT_framebuffer_multisample = true; ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true; - ctx->Extensions.EXT_polygon_offset_clamp = true; ctx->Extensions.EXT_transform_feedback = true; ctx->Extensions.OES_depth_texture_cube_map = true; -- 2.30.2