From dbc208395deab2d2470b859d935c6a71595b6af9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 17 Sep 2012 15:27:37 +0200 Subject: [PATCH] use of new migen clock_domains convention --- examples/de0_nano/constraints.py | 4 ++-- examples/de0_nano/top.py | 17 +++++++++-------- examples/de1/constraints.py | 8 ++++---- examples/de1/top.py | 14 +++++++------- 4 files changed, 22 insertions(+), 21 deletions(-) diff --git a/examples/de0_nano/constraints.py b/examples/de0_nano/constraints.py index 6852f70f..b780de21 100644 --- a/examples/de0_nano/constraints.py +++ b/examples/de0_nano/constraints.py @@ -1,5 +1,5 @@ class Constraints: - def __init__(self, in_clk, in_rst_n, spi2csr0, led0): + def __init__(self, in_rst_n, cd_in, spi2csr0, led0): self.constraints = [] def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""): self.constraints.append((signal, vec, pin, iostandard, extra,sch)) @@ -10,7 +10,7 @@ class Constraints: add(signal, p, i, iostandard, extra) i += 1 # sys_clk - add(in_clk, "R8") # CLOCK_50 + add(cd_in.clk, "R8") # CLOCK_50 # sys_rst add(in_rst_n, "J15") # KEY[0] diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 8e007f6b..a4701031 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -81,6 +81,7 @@ def get(): # Trigger term0 = trigger.Term(trig_width) + trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0]) # Recorder @@ -120,7 +121,6 @@ def get(): ] sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)] - print(sinus) sinus_re = Signal() sinus_gen = Signal(BV(8)) comb +=[sinus_re.eq(1)] @@ -158,22 +158,23 @@ def get(): recorder0.trig_hit.eq(trigger0.hit) ] - + # HouseKeeping - in_clk = Signal() + cd_in = ClockDomain("in") in_rst_n = Signal() - in_rst = Signal() comb += [ - in_rst.eq(~in_rst_n) + cd_in.rst.eq(~in_rst_n) ] + frag = autofragment.from_local() frag += Fragment(sync=sync,comb=comb,memories=[sinus_mem]) - cst = Constraints(in_clk, in_rst_n, spi2csr0, led0) + cst = Constraints(in_rst_n, cd_in, spi2csr0, led0) src_verilog, vns = verilog.convert(frag, cst.get_ios(), name="de1", - clk_signal = in_clk, - rst_signal = in_rst, + clock_domains={ + "sys": cd_in + }, return_ns=True) src_qsf = cst.get_qsf(vns) return (src_verilog, src_qsf) \ No newline at end of file diff --git a/examples/de1/constraints.py b/examples/de1/constraints.py index 2e8d2ee3..421fdd4d 100644 --- a/examples/de1/constraints.py +++ b/examples/de1/constraints.py @@ -1,5 +1,5 @@ class Constraints: - def __init__(self, in_clk, in_rst_n, spi2csr0, led0, sw0): + def __init__(self, in_rst_n, cd_in, spi2csr0, led0, sw0): self.constraints = [] def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""): self.constraints.append((signal, vec, pin, iostandard, extra,sch)) @@ -10,11 +10,11 @@ class Constraints: add(signal, p, i, iostandard, extra) i += 1 # sys_clk - add(in_clk, "L1") # CLOCK_50 + add(cd_in.clk, "L1") # CLOCK_50 # sys_rst - add(in_rst_n, "R22") # KEY[0] - + add(in_rst_n, "R22") # KEY[0] + # spi2csr0 add(spi2csr0.spi_clk, "F13") #GPIO_1[9] add(spi2csr0.spi_cs_n, "G15") #GPIO_1[3] diff --git a/examples/de1/top.py b/examples/de1/top.py index 511db3c0..10d1fd93 100644 --- a/examples/de1/top.py +++ b/examples/de1/top.py @@ -121,7 +121,6 @@ def get(): ] sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)] - print(sinus) sinus_re = Signal() sinus_gen = Signal(BV(8)) comb +=[sinus_re.eq(1)] @@ -164,20 +163,21 @@ def get(): # HouseKeeping - in_clk = Signal() + cd_in = ClockDomain("in") in_rst_n = Signal() - in_rst = Signal() comb += [ - in_rst.eq(~in_rst_n) + cd_in.rst.eq(~in_rst_n) ] + frag = autofragment.from_local() frag += Fragment(sync=sync,comb=comb,memories=[sinus_mem]) - cst = Constraints(in_clk, in_rst_n, spi2csr0, led0, sw0) + cst = Constraints(in_rst_n, cd_in, spi2csr0, led0, sw0) src_verilog, vns = verilog.convert(frag, cst.get_ios(), name="de1", - clk_signal = in_clk, - rst_signal = in_rst, + clock_domains={ + "sys": cd_in + }, return_ns=True) src_qsf = cst.get_qsf(vns) return (src_verilog, src_qsf) \ No newline at end of file -- 2.30.2