From dbc3d7a15bd8db75dc9411d698b1b5fc8fb173f5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 19:34:05 +0000 Subject: [PATCH] fix up shift_rot test_pipe_caller to new regspeckls style --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index 67f7d9ba..cfa1c674 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -71,7 +71,10 @@ def set_alu_inputs(alu, dec2, sim): class ShiftRotIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=None) + class PPspec: + XLEN = 64 + pps = PPspec() + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=pps) pspec.draft_bitmanip = True alu = ShiftRotBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) @@ -138,7 +141,10 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) pdecode = pdecode2.dec - pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=None) + class PPspec: + XLEN = 64 + pps = PPspec() + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=pps) pspec.draft_bitmanip = True m.submodules.alu = alu = ShiftRotBasePipe(pspec) -- 2.30.2