From dc037cdb8c2a587cb7e45507cc24c05faf4c41d3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Jul 2020 11:30:30 +0100 Subject: [PATCH] not perfect but close enough: add read registers RA/S/B/C in parser --- libreriscv | 2 +- src/soc/decoder/pseudo/parser.py | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/libreriscv b/libreriscv index fbdd3574..cde4b651 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit fbdd3574edccf1fa79b5181470bf7d8d00cea8df +Subproject commit cde4b6519f6f23520899e1c1bba71548746015ec diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py index 8c6a1f2e..9da2f372 100644 --- a/src/soc/decoder/pseudo/parser.py +++ b/src/soc/decoder/pseudo/parser.py @@ -663,6 +663,11 @@ class PowerParser: self.op_fields.add(name) if name == 'overflow': self.write_regs.add(name) + # XXX yuk. this results in extraneous registers being added. + # really should be analysing slice (Assign) and working out if + # the variable being sliced is a GPR. + if name in ['RA', 'RS', 'RB', 'RC']: + self.read_regs.add(name) # add to list of regs to read if self.include_ca_in_write: if name in ['CA', 'CA32']: self.write_regs.add(name) -- 2.30.2