From dc0fda8ed29fca0d8c8fbd81236ac529a834ca29 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 22 Feb 2021 04:15:56 +0000 Subject: [PATCH] --- openpower/sv/implementation.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn index 20ad7d325..c2018946d 100644 --- a/openpower/sv/implementation.mdwn +++ b/openpower/sv/implementation.mdwn @@ -149,7 +149,7 @@ When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) TODO. INTs, FPs, CRs, these all increase to 128. Welcome To Vector ISAs. -At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP svslar may also be adjusted. +At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted. ## Single Predication -- 2.30.2