From dc355223e465d3a2c090f34afd2ce965d20de199 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Wed, 19 Dec 2018 14:54:08 +0100 Subject: [PATCH] Restrict a VSX extract to TARGET_POWERPC64 (PR88213) This pattern optimises a scalar extract from a vector loaded from memory to be just a scalar load from memory. But to do a 64-bit integer load you need 64-bit integer registers, which needs TARGET_POWERPC64. PR target/88213 * config/rs6000/vsx.md (*vsx_extract___load): Require TARGET_POWERPC64. From-SVN: r267263 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/vsx.md | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 56e50e2cbfb..6fe6ec342c1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-12-19 Segher Boessenkool + + PR target/88213 + * config/rs6000/vsx.md (*vsx_extract___load): + Require TARGET_POWERPC64. + 2018-12-19 Richard Biener PR tree-optimization/88533 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 65a9892ff9f..38223a57365 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3257,7 +3257,7 @@ (match_operand:VSX_D 1 "memory_operand" "m,m") (parallel [(match_operand:QI 2 "const_0_to_1_operand" "n,n")]))) (clobber (match_scratch:P 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (mode)" + "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode)" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] -- 2.30.2