From dc3a864af70e9b227771219d6b5a53296e10b78c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 30 Aug 2020 10:51:30 +0100 Subject: [PATCH] set mul post_stage o.ok only when needed, and fix xer_so pass-through https://bugs.libre-soc.org/show_bug.cgi?id=482 --- src/soc/fu/mul/post_stage.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py index dbe560e9..14d2d911 100644 --- a/src/soc/fu/mul/post_stage.py +++ b/src/soc/fu/mul/post_stage.py @@ -39,20 +39,22 @@ class MulMainStage3(PipeModBase): # check negate: select signed/unsigned mul_o = Signal(o_i.width, reset_less=True) comb += mul_o.eq(Mux(self.i.neg_res, -o_i, o_i)) - comb += o.ok.eq(1) # OP_MUL_nnn - select hi32/hi64/lo64 from result with m.Switch(op.insn_type): # hi-32 replicated twice with m.Case(MicrOp.OP_MUL_H32): comb += o.data.eq(Repl(mul_o[32:64], 2)) + comb += o.ok.eq(1) # hi-64 with m.Case(MicrOp.OP_MUL_H64): comb += o.data.eq(mul_o[64:128]) + comb += o.ok.eq(1) # lo-64 - overflow - with m.Default(): + with m.Case(MicrOp.OP_MUL_L64): # take the low 64 bits of the mul comb += o.data.eq(mul_o[0:64]) + comb += o.ok.eq(1) # compute overflow 32/64 mul_ov = Signal(reset_less=True) @@ -73,7 +75,7 @@ class MulMainStage3(PipeModBase): ###### sticky overflow and context, both pass-through ##### - comb += self.o.xer_so.data.eq(self.i.xer_so) + comb += self.o.xer_so.eq(self.i.xer_so) comb += self.o.ctx.eq(self.i.ctx) return m -- 2.30.2