From dc40b391214d02271d9d0d5013872dbfc4df8499 Mon Sep 17 00:00:00 2001 From: Fred Fish Date: Mon, 24 Feb 1997 18:25:19 +0000 Subject: [PATCH] * gas/tic80/{add.d, bitnum.d, ccode.d, cregops.d, endmask.d, regops.d, relocs1.d, (relocs1.c): Add file for reference. (relocs1b.d): Split reloc table contents test to different test file. (relocs2.c): Add test that uses various types (char, short, int, ...) of static and global variables with data shuffling to generate lots of ld/st instructions for the different types. (relocs2.d): New file, expected code for relocs2 test. (relocs2.lst): New file, TI assembler listing for reference. (relocs2.s): New file, assembly source for relocs2 test. (relocs2b.d): New file, expected reloc table contents for relocs2 test. (tic80.exp): Run the relocs1b, relocs2, and relocs2b tests. --- gas/testsuite/ChangeLog | 16 ++ gas/testsuite/gas/tic80/add.d | 46 ++-- gas/testsuite/gas/tic80/bitnum.d | 150 ++++++------ gas/testsuite/gas/tic80/ccode.d | 50 ++-- gas/testsuite/gas/tic80/cregops.d | 122 +++++----- gas/testsuite/gas/tic80/endmask.d | 68 +++--- gas/testsuite/gas/tic80/regops.d | 362 ++++++++++++++-------------- gas/testsuite/gas/tic80/relocs1.c | 28 +++ gas/testsuite/gas/tic80/relocs1.d | 104 ++++---- gas/testsuite/gas/tic80/relocs1b.d | 12 + gas/testsuite/gas/tic80/relocs2.c | 41 ++++ gas/testsuite/gas/tic80/relocs2.d | 65 +++++ gas/testsuite/gas/tic80/relocs2.lst | 112 +++++++++ gas/testsuite/gas/tic80/relocs2.s | 72 ++++++ gas/testsuite/gas/tic80/relocs2b.d | 38 +++ gas/testsuite/gas/tic80/tic80.exp | 3 + 16 files changed, 836 insertions(+), 453 deletions(-) create mode 100644 gas/testsuite/gas/tic80/relocs1.c create mode 100644 gas/testsuite/gas/tic80/relocs1b.d create mode 100644 gas/testsuite/gas/tic80/relocs2.c create mode 100644 gas/testsuite/gas/tic80/relocs2.d create mode 100644 gas/testsuite/gas/tic80/relocs2.lst create mode 100644 gas/testsuite/gas/tic80/relocs2.s create mode 100644 gas/testsuite/gas/tic80/relocs2b.d diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 1dd761b0b9d..0723d0ac382 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,4 +1,20 @@ +start-sanitize-tic80 +Mon Feb 24 10:40:28 1997 Fred Fish + + * gas/tic80/{add.d, bitnum.d, ccode.d, cregops.d, endmask.d, + regops.d, relocs1.d, + (relocs1.c): Add file for reference. + (relocs1b.d): Split reloc table contents test to different test file. + (relocs2.c): Add test that uses various types (char, short, int, ...) of + static and global variables with data shuffling to generate lots of ld/st + instructions for the different types. + (relocs2.d): New file, expected code for relocs2 test. + (relocs2.lst): New file, TI assembler listing for reference. + (relocs2.s): New file, assembly source for relocs2 test. + (relocs2b.d): New file, expected reloc table contents for relocs2 test. + (tic80.exp): Run the relocs1b, relocs2, and relocs2b tests. +end-sanitize-tic80 Sun Feb 23 17:54:00 1997 Dawn Perchik * gas/all/itbl-test.c(main): Update function calls. diff --git a/gas/testsuite/gas/tic80/add.d b/gas/testsuite/gas/tic80/add.d index 184d9f9fa7a..cfce1ca1865 100644 --- a/gas/testsuite/gas/tic80/add.d +++ b/gas/testsuite/gas/tic80/add.d @@ -1,4 +1,4 @@ -#objdump: -dr +#objdump: -d #name: TIc80 signed and unsigned add instructions .*: +file format .*tic80.* @@ -6,25 +6,25 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0a 00 fb 62 add r10,r11,r12 - 4: ff 3f ac 20 add 0x3fff,r2,r4 - 8: 00 40 2c 21 add 0xffffc000,r4,r4 - c: 00 10 7b 31 add 0x4000,r5,r6 - 10: 00 40 00 00 - 14: 00 10 fb 41 add 0xffffbfff,r7,r8 - 18: ff bf ff ff - 1c: 00 10 bb 5a add 0x7fffffff,r10,r11 - 20: ff ff ff 7f - 24: 00 10 3b 6b add 0x80000000,r12,r13 - 28: 00 00 00 80 - 2c: 0a 20 fb 62 addu r10,r11,r12 - 30: ff bf ac 20 addu 0x3fff,r2,r4 - 34: 00 c0 2c 21 addu 0xffffc000,r4,r4 - 38: 00 30 7b 31 addu 0x4000,r5,r6 - 3c: 00 40 00 00 - 40: 00 30 fb 41 addu 0xffffbfff,r7,r8 - 44: ff bf ff ff - 48: 00 30 bb 5a addu 0x7fffffff,r10,r11 - 4c: ff ff ff 7f - 50: 00 30 3b 6b addu 0x80000000,r12,r13 - 54: 00 00 00 80 + 0: 0a 00 fb 62.* + 4: ff 3f ac 20.* + 8: 00 40 2c 21.* + c: 00 10 7b 31.* + 10: 00 40 00 00.* + 14: 00 10 fb 41.* + 18: ff bf ff ff.* + 1c: 00 10 bb 5a.* + 20: ff ff ff 7f.* + 24: 00 10 3b 6b.* + 28: 00 00 00 80.* + 2c: 0a 20 fb 62.* + 30: ff bf ac 20.* + 34: 00 c0 2c 21.* + 38: 00 30 7b 31.* + 3c: 00 40 00 00.* + 40: 00 30 fb 41.* + 44: ff bf ff ff.* + 48: 00 30 bb 5a.* + 4c: ff ff ff 7f.* + 50: 00 30 3b 6b.* + 54: 00 00 00 80.* diff --git a/gas/testsuite/gas/tic80/bitnum.d b/gas/testsuite/gas/tic80/bitnum.d index ce51aa21eb6..fcaee8b086b 100644 --- a/gas/testsuite/gas/tic80/bitnum.d +++ b/gas/testsuite/gas/tic80/bitnum.d @@ -1,4 +1,4 @@ -#objdump: -dr +#objdump: -d #name: TIc80 coverage of symbolic BITNUM values .*: +file format .*tic80.* @@ -6,77 +6,77 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0a 40 39 fa bbo r10,r8,eq\.b - 4: 0a 40 39 f2 bbo r10,r8,ne\.b - 8: 0a 40 39 ea bbo r10,r8,gt\.b - c: 0a 40 39 e2 bbo r10,r8,le\.b - 10: 0a 40 39 da bbo r10,r8,lt\.b - 14: 0a 40 39 d2 bbo r10,r8,ge\.b - 18: 0a 40 39 ca bbo r10,r8,hi\.b - 1c: 0a 40 39 c2 bbo r10,r8,ls\.b - 20: 0a 40 39 ba bbo r10,r8,lo\.b - 24: 0a 40 39 b2 bbo r10,r8,hs\.b - 28: 0a 40 39 aa bbo r10,r8,eq\.h - 2c: 0a 40 39 a2 bbo r10,r8,ne\.h - 30: 0a 40 39 9a bbo r10,r8,gt\.h - 34: 0a 40 39 92 bbo r10,r8,le\.h - 38: 0a 40 39 8a bbo r10,r8,lt\.h - 3c: 0a 40 39 82 bbo r10,r8,ge\.h - 40: 0a 40 39 7a bbo r10,r8,hi\.h - 44: 0a 40 39 72 bbo r10,r8,ls\.h - 48: 0a 40 39 6a bbo r10,r8,lo\.h - 4c: 0a 40 39 62 bbo r10,r8,hs\.h - 50: 0a 40 39 5a bbo r10,r8,eq\.f - 54: 0a 40 39 52 bbo r10,r8,ne\.f - 58: 0a 40 39 4a bbo r10,r8,gt\.f - 5c: 0a 40 39 42 bbo r10,r8,le\.f - 60: 0a 40 39 3a bbo r10,r8,lt\.f - 64: 0a 40 39 32 bbo r10,r8,ge\.f - 68: 0a 40 39 2a bbo r10,r8,hi\.w - 6c: 0a 40 39 22 bbo r10,r8,in\.f - 70: 0a 40 39 1a bbo r10,r8,ib\.f - 74: 0a 40 39 12 bbo r10,r8,hs\.w - 78: 0a 40 39 5a bbo r10,r8,eq\.f - 7c: 0a 40 39 52 bbo r10,r8,ne\.f - 80: 0a 40 39 4a bbo r10,r8,gt\.f - 84: 0a 40 39 42 bbo r10,r8,le\.f - 88: 0a 40 39 3a bbo r10,r8,lt\.f - 8c: 0a 40 39 32 bbo r10,r8,ge\.f - 90: 0a 40 39 2a bbo r10,r8,hi\.w - 94: 0a 40 39 22 bbo r10,r8,in\.f - 98: 0a 40 39 1a bbo r10,r8,ib\.f - 9c: 0a 40 39 12 bbo r10,r8,hs\.w - a0: 0a 40 39 0a bbo r10,r8,uo\.f - a4: 0a 40 39 02 bbo r10,r8,or\.f - a8: 0a 40 39 fa bbo r10,r8,eq\.b - ac: 0a 40 39 f2 bbo r10,r8,ne\.b - b0: 0a 40 39 ea bbo r10,r8,gt\.b - b4: 0a 40 39 e2 bbo r10,r8,le\.b - b8: 0a 40 39 da bbo r10,r8,lt\.b - bc: 0a 40 39 d2 bbo r10,r8,ge\.b - c0: 0a 40 39 ca bbo r10,r8,hi\.b - c4: 0a 40 39 c2 bbo r10,r8,ls\.b - c8: 0a 40 39 ba bbo r10,r8,lo\.b - cc: 0a 40 39 b2 bbo r10,r8,hs\.b - d0: 0a 40 39 aa bbo r10,r8,eq\.h - d4: 0a 40 39 a2 bbo r10,r8,ne\.h - d8: 0a 40 39 9a bbo r10,r8,gt\.h - dc: 0a 40 39 92 bbo r10,r8,le\.h - e0: 0a 40 39 8a bbo r10,r8,lt\.h - e4: 0a 40 39 82 bbo r10,r8,ge\.h - e8: 0a 40 39 7a bbo r10,r8,hi\.h - ec: 0a 40 39 72 bbo r10,r8,ls\.h - f0: 0a 40 39 6a bbo r10,r8,lo\.h - f4: 0a 40 39 62 bbo r10,r8,hs\.h - f8: 0a 40 39 5a bbo r10,r8,eq\.f - fc: 0a 40 39 52 bbo r10,r8,ne\.f - 100: 0a 40 39 4a bbo r10,r8,gt\.f - 104: 0a 40 39 42 bbo r10,r8,le\.f - 108: 0a 40 39 3a bbo r10,r8,lt\.f - 10c: 0a 40 39 32 bbo r10,r8,ge\.f - 110: 0a 40 39 2a bbo r10,r8,hi\.w - 114: 0a 40 39 22 bbo r10,r8,in\.f - 118: 0a 40 39 1a bbo r10,r8,ib\.f - 11c: 0a 40 39 12 bbo r10,r8,hs\.w - 120: 0a 40 39 0a bbo r10,r8,uo\.f - 124: 0a 40 39 02 bbo r10,r8,or\.f + 0: 0a 40 39 fa.* + 4: 0a 40 39 f2.* + 8: 0a 40 39 ea.* + c: 0a 40 39 e2.* + 10: 0a 40 39 da.* + 14: 0a 40 39 d2.* + 18: 0a 40 39 ca.* + 1c: 0a 40 39 c2.* + 20: 0a 40 39 ba.* + 24: 0a 40 39 b2.* + 28: 0a 40 39 aa.* + 2c: 0a 40 39 a2.* + 30: 0a 40 39 9a.* + 34: 0a 40 39 92.* + 38: 0a 40 39 8a.* + 3c: 0a 40 39 82.* + 40: 0a 40 39 7a.* + 44: 0a 40 39 72.* + 48: 0a 40 39 6a.* + 4c: 0a 40 39 62.* + 50: 0a 40 39 5a.* + 54: 0a 40 39 52.* + 58: 0a 40 39 4a.* + 5c: 0a 40 39 42.* + 60: 0a 40 39 3a.* + 64: 0a 40 39 32.* + 68: 0a 40 39 2a.* + 6c: 0a 40 39 22.* + 70: 0a 40 39 1a.* + 74: 0a 40 39 12.* + 78: 0a 40 39 5a.* + 7c: 0a 40 39 52.* + 80: 0a 40 39 4a.* + 84: 0a 40 39 42.* + 88: 0a 40 39 3a.* + 8c: 0a 40 39 32.* + 90: 0a 40 39 2a.* + 94: 0a 40 39 22.* + 98: 0a 40 39 1a.* + 9c: 0a 40 39 12.* + a0: 0a 40 39 0a.* + a4: 0a 40 39 02.* + a8: 0a 40 39 fa.* + ac: 0a 40 39 f2.* + b0: 0a 40 39 ea.* + b4: 0a 40 39 e2.* + b8: 0a 40 39 da.* + bc: 0a 40 39 d2.* + c0: 0a 40 39 ca.* + c4: 0a 40 39 c2.* + c8: 0a 40 39 ba.* + cc: 0a 40 39 b2.* + d0: 0a 40 39 aa.* + d4: 0a 40 39 a2.* + d8: 0a 40 39 9a.* + dc: 0a 40 39 92.* + e0: 0a 40 39 8a.* + e4: 0a 40 39 82.* + e8: 0a 40 39 7a.* + ec: 0a 40 39 72.* + f0: 0a 40 39 6a.* + f4: 0a 40 39 62.* + f8: 0a 40 39 5a.* + fc: 0a 40 39 52.* + 100: 0a 40 39 4a.* + 104: 0a 40 39 42.* + 108: 0a 40 39 3a.* + 10c: 0a 40 39 32.* + 110: 0a 40 39 2a.* + 114: 0a 40 39 22.* + 118: 0a 40 39 1a.* + 11c: 0a 40 39 12.* + 120: 0a 40 39 0a.* + 124: 0a 40 39 02.* diff --git a/gas/testsuite/gas/tic80/ccode.d b/gas/testsuite/gas/tic80/ccode.d index 54140da1e72..b5a38aa7d05 100644 --- a/gas/testsuite/gas/tic80/ccode.d +++ b/gas/testsuite/gas/tic80/ccode.d @@ -1,4 +1,4 @@ -#objdump: -dr +#objdump: -d #name: TIc80 coverage of symbolic condition code values .*: +file format .*tic80.* @@ -6,27 +6,27 @@ Disassembly of section .text: 00000000 <.text>: - 0: 07 a0 79 01 bcnd\.a r7,r5,nev\.b - 4: 07 a0 79 09 bcnd\.a r7,r5,gt0\.b - 8: 07 a0 79 11 bcnd\.a r7,r5,eq0\.b - c: 07 a0 79 19 bcnd\.a r7,r5,ge0\.b - 10: 07 a0 79 21 bcnd\.a r7,r5,lt0\.b - 14: 07 a0 79 29 bcnd\.a r7,r5,ne0\.b - 18: 07 a0 79 31 bcnd\.a r7,r5,le0\.b - 1c: 07 a0 79 39 bcnd\.a r7,r5,alw\.b - 20: 07 a0 79 41 bcnd\.a r7,r5,nev\.h - 24: 07 a0 79 49 bcnd\.a r7,r5,gt0\.h - 28: 07 a0 79 51 bcnd\.a r7,r5,eq0\.h - 2c: 07 a0 79 59 bcnd\.a r7,r5,ge0\.h - 30: 07 a0 79 61 bcnd\.a r7,r5,lt0\.h - 34: 07 a0 79 69 bcnd\.a r7,r5,ne0\.h - 38: 07 a0 79 71 bcnd\.a r7,r5,le0\.h - 3c: 07 a0 79 79 bcnd\.a r7,r5,alw\.h - 40: 07 a0 79 81 bcnd\.a r7,r5,nev\.w - 44: 07 a0 79 89 bcnd\.a r7,r5,gt0\.w - 48: 07 a0 79 91 bcnd\.a r7,r5,eq0\.w - 4c: 07 a0 79 99 bcnd\.a r7,r5,ge0\.w - 50: 07 a0 79 a1 bcnd\.a r7,r5,lt0\.w - 54: 07 a0 79 a9 bcnd\.a r7,r5,ne0\.w - 58: 07 a0 79 b1 bcnd\.a r7,r5,le0\.w - 5c: 07 a0 79 b9 bcnd\.a r7,r5,alw\.w + 0: 07 a0 79 01.* + 4: 07 a0 79 09.* + 8: 07 a0 79 11.* + c: 07 a0 79 19.* + 10: 07 a0 79 21.* + 14: 07 a0 79 29.* + 18: 07 a0 79 31.* + 1c: 07 a0 79 39.* + 20: 07 a0 79 41.* + 24: 07 a0 79 49.* + 28: 07 a0 79 51.* + 2c: 07 a0 79 59.* + 30: 07 a0 79 61.* + 34: 07 a0 79 69.* + 38: 07 a0 79 71.* + 3c: 07 a0 79 79.* + 40: 07 a0 79 81.* + 44: 07 a0 79 89.* + 48: 07 a0 79 91.* + 4c: 07 a0 79 99.* + 50: 07 a0 79 a1.* + 54: 07 a0 79 a9.* + 58: 07 a0 79 b1.* + 5c: 07 a0 79 b9.* diff --git a/gas/testsuite/gas/tic80/cregops.d b/gas/testsuite/gas/tic80/cregops.d index 5877c0f4e92..44b61e98c13 100644 --- a/gas/testsuite/gas/tic80/cregops.d +++ b/gas/testsuite/gas/tic80/cregops.d @@ -1,4 +1,4 @@ -#objdump: -dr +#objdump: -d #name: TIc80 control register operands .*: +file format .*tic80.* @@ -6,63 +6,63 @@ Disassembly of section .text: 00000000 <.text>: - 0: 34 00 02 10 rdcr ANASTAT,r2 - 4: 39 00 02 10 rdcr BRK1,r2 - 8: 3a 00 02 10 rdcr BRK2,r2 - c: 02 00 02 10 rdcr CONFIG,r2 - 10: 00 05 02 10 rdcr DLRU,r2 - 14: 00 04 02 10 rdcr DTAG0,r2 - 18: 01 04 02 10 rdcr DTAG1,r2 - 1c: 0a 04 02 10 rdcr DTAG10,r2 - 20: 0b 04 02 10 rdcr DTAG11,r2 - 24: 0c 04 02 10 rdcr DTAG12,r2 - 28: 0d 04 02 10 rdcr DTAG13,r2 - 2c: 0e 04 02 10 rdcr DTAG14,r2 - 30: 0f 04 02 10 rdcr DTAG15,r2 - 34: 02 04 02 10 rdcr DTAG2,r2 - 38: 03 04 02 10 rdcr DTAG3,r2 - 3c: 04 04 02 10 rdcr DTAG4,r2 - 40: 05 04 02 10 rdcr DTAG5,r2 - 44: 06 04 02 10 rdcr DTAG6,r2 - 48: 07 04 02 10 rdcr DTAG7,r2 - 4c: 08 04 02 10 rdcr DTAG8,r2 - 50: 09 04 02 10 rdcr DTAG9,r2 - 54: 33 00 02 10 rdcr ECOMCNTL,r2 - 58: 01 00 02 10 rdcr EIP,r2 - 5c: 00 00 02 10 rdcr EPC,r2 - 60: 11 00 02 10 rdcr FLTADR,r2 - 64: 14 00 02 10 rdcr FLTDTH,r2 - 68: 13 00 02 10 rdcr FLTDTL,r2 - 6c: 10 00 02 10 rdcr FLTOP,r2 - 70: 12 00 02 10 rdcr FLTTAG,r2 - 74: 08 00 02 10 rdcr FPST,r2 - 78: 06 00 02 10 rdcr IE,r2 - 7c: 00 03 02 10 rdcr ILRU,r2 - 80: 00 40 02 10 rdcr IN0P,r2 - 84: 01 40 02 10 rdcr IN1P,r2 - 88: 04 00 02 10 rdcr INTPEN,r2 - 8c: 00 02 02 10 rdcr ITAG0,r2 - 90: 01 02 02 10 rdcr ITAG1,r2 - 94: 0a 02 02 10 rdcr ITAG10,r2 - 98: 0b 02 02 10 rdcr ITAG11,r2 - 9c: 0c 02 02 10 rdcr ITAG12,r2 - a0: 0d 02 02 10 rdcr ITAG13,r2 - a4: 0e 02 02 10 rdcr ITAG14,r2 - a8: 0f 02 02 10 rdcr ITAG15,r2 - ac: 02 02 02 10 rdcr ITAG2,r2 - b0: 03 02 02 10 rdcr ITAG3,r2 - b4: 04 02 02 10 rdcr ITAG4,r2 - b8: 05 02 02 10 rdcr ITAG5,r2 - bc: 06 02 02 10 rdcr ITAG6,r2 - c0: 07 02 02 10 rdcr ITAG7,r2 - c4: 08 02 02 10 rdcr ITAG8,r2 - c8: 09 02 02 10 rdcr ITAG9,r2 - cc: 31 00 02 10 rdcr MIP,r2 - d0: 30 00 02 10 rdcr MPC,r2 - d4: 02 40 02 10 rdcr OUTP,r2 - d8: 0d 00 02 10 rdcr PKTREQ,r2 - dc: 0a 00 02 10 rdcr PPERROR,r2 - e0: 20 00 02 10 rdcr SYSSTK,r2 - e4: 21 00 02 10 rdcr SYSTMP,r2 - e8: 0e 00 02 10 rdcr TCOUNT,r2 - ec: 0f 00 02 10 rdcr TSCALE,r2 + 0: 34 00 02 10.* + 4: 39 00 02 10.* + 8: 3a 00 02 10.* + c: 02 00 02 10.* + 10: 00 05 02 10.* + 14: 00 04 02 10.* + 18: 01 04 02 10.* + 1c: 0a 04 02 10.* + 20: 0b 04 02 10.* + 24: 0c 04 02 10.* + 28: 0d 04 02 10.* + 2c: 0e 04 02 10.* + 30: 0f 04 02 10.* + 34: 02 04 02 10.* + 38: 03 04 02 10.* + 3c: 04 04 02 10.* + 40: 05 04 02 10.* + 44: 06 04 02 10.* + 48: 07 04 02 10.* + 4c: 08 04 02 10.* + 50: 09 04 02 10.* + 54: 33 00 02 10.* + 58: 01 00 02 10.* + 5c: 00 00 02 10.* + 60: 11 00 02 10.* + 64: 14 00 02 10.* + 68: 13 00 02 10.* + 6c: 10 00 02 10.* + 70: 12 00 02 10.* + 74: 08 00 02 10.* + 78: 06 00 02 10.* + 7c: 00 03 02 10.* + 80: 00 40 02 10.* + 84: 01 40 02 10.* + 88: 04 00 02 10.* + 8c: 00 02 02 10.* + 90: 01 02 02 10.* + 94: 0a 02 02 10.* + 98: 0b 02 02 10.* + 9c: 0c 02 02 10.* + a0: 0d 02 02 10.* + a4: 0e 02 02 10.* + a8: 0f 02 02 10.* + ac: 02 02 02 10.* + b0: 03 02 02 10.* + b4: 04 02 02 10.* + b8: 05 02 02 10.* + bc: 06 02 02 10.* + c0: 07 02 02 10.* + c4: 08 02 02 10.* + c8: 09 02 02 10.* + cc: 31 00 02 10.* + d0: 30 00 02 10.* + d4: 02 40 02 10.* + d8: 0d 00 02 10.* + dc: 0a 00 02 10.* + e0: 20 00 02 10.* + e4: 21 00 02 10.* + e8: 0e 00 02 10.* + ec: 0f 00 02 10.* diff --git a/gas/testsuite/gas/tic80/endmask.d b/gas/testsuite/gas/tic80/endmask.d index 2d79c137f02..5cd08471113 100644 --- a/gas/testsuite/gas/tic80/endmask.d +++ b/gas/testsuite/gas/tic80/endmask.d @@ -1,4 +1,4 @@ -#objdump: -dr +#objdump: -d #name: TIc80 coverage of shift instruction ENDMASK field .*: +file format .*tic80.* @@ -6,36 +6,36 @@ Disassembly of section .text: 00000000 <.text>: - 0: 05 00 c7 49 shl 5,0,r7,r9 - 4: 25 00 c7 49 shl 5,1,r7,r9 - 8: 45 00 c7 49 shl 5,2,r7,r9 - c: 65 00 c7 49 shl 5,3,r7,r9 - 10: 85 00 c7 49 shl 5,4,r7,r9 - 14: a5 00 c7 49 shl 5,5,r7,r9 - 18: c5 00 c7 49 shl 5,6,r7,r9 - 1c: e5 00 c7 49 shl 5,7,r7,r9 - 20: 05 01 c7 49 shl 5,8,r7,r9 - 24: 25 01 c7 49 shl 5,9,r7,r9 - 28: 45 01 c7 49 shl 5,10,r7,r9 - 2c: 65 01 c7 49 shl 5,11,r7,r9 - 30: 85 01 c7 49 shl 5,12,r7,r9 - 34: a5 01 c7 49 shl 5,13,r7,r9 - 38: c5 01 c7 49 shl 5,14,r7,r9 - 3c: e5 01 c7 49 shl 5,15,r7,r9 - 40: 05 02 c7 49 shl 5,16,r7,r9 - 44: 25 02 c7 49 shl 5,17,r7,r9 - 48: 45 02 c7 49 shl 5,18,r7,r9 - 4c: 65 02 c7 49 shl 5,19,r7,r9 - 50: 85 02 c7 49 shl 5,20,r7,r9 - 54: a5 02 c7 49 shl 5,21,r7,r9 - 58: c5 02 c7 49 shl 5,22,r7,r9 - 5c: e5 02 c7 49 shl 5,23,r7,r9 - 60: 05 03 c7 49 shl 5,24,r7,r9 - 64: 25 03 c7 49 shl 5,25,r7,r9 - 68: 45 03 c7 49 shl 5,26,r7,r9 - 6c: 65 03 c7 49 shl 5,27,r7,r9 - 70: 85 03 c7 49 shl 5,28,r7,r9 - 74: a5 03 c7 49 shl 5,29,r7,r9 - 78: c5 03 c7 49 shl 5,30,r7,r9 - 7c: e5 03 c7 49 shl 5,31,r7,r9 - 80: 05 00 c7 49 shl 5,0,r7,r9 + 0: 05 00 c7 49.* + 4: 25 00 c7 49.* + 8: 45 00 c7 49.* + c: 65 00 c7 49.* + 10: 85 00 c7 49.* + 14: a5 00 c7 49.* + 18: c5 00 c7 49.* + 1c: e5 00 c7 49.* + 20: 05 01 c7 49.* + 24: 25 01 c7 49.* + 28: 45 01 c7 49.* + 2c: 65 01 c7 49.* + 30: 85 01 c7 49.* + 34: a5 01 c7 49.* + 38: c5 01 c7 49.* + 3c: e5 01 c7 49.* + 40: 05 02 c7 49.* + 44: 25 02 c7 49.* + 48: 45 02 c7 49.* + 4c: 65 02 c7 49.* + 50: 85 02 c7 49.* + 54: a5 02 c7 49.* + 58: c5 02 c7 49.* + 5c: e5 02 c7 49.* + 60: 05 03 c7 49.* + 64: 25 03 c7 49.* + 68: 45 03 c7 49.* + 6c: 65 03 c7 49.* + 70: 85 03 c7 49.* + 74: a5 03 c7 49.* + 78: c5 03 c7 49.* + 7c: e5 03 c7 49.* + 80: 05 00 c7 49.* diff --git a/gas/testsuite/gas/tic80/regops.d b/gas/testsuite/gas/tic80/regops.d index 0df4349a144..dd0fa85753c 100644 --- a/gas/testsuite/gas/tic80/regops.d +++ b/gas/testsuite/gas/tic80/regops.d @@ -1,4 +1,4 @@ -#objdump: -dr +#objdump: -d #name: TIc80 register operands .*: +file format .*tic80.* @@ -6,183 +6,183 @@ Disassembly of section .text: 00000000 <.text>: - 0: 03 00 3b 29 add r3,r4,r5 - 4: 03 20 3b 29 addu r3,r4,r5 - 8: 05 20 32 11 and r5,r4,r2 - c: 05 20 32 11 and r5,r4,r2 - 10: 0a 00 33 73 and\.ff r10,r12,r14 - 14: 0a 80 32 73 and\.ft r10,r12,r14 - 18: 0a 40 32 73 and\.tf r10,r12,r14 - 1c: 0a 40 39 1a bbo r10,r8,ib\.f - 20: 0a 60 39 fa bbo\.a r10,r8,eq\.b - 24: 0a 00 39 22 bbz r10,r8,in\.f - 28: 0a 20 39 2a bbz\.a r10,r8,hi\.w - 2c: 04 80 b9 21 bcnd r4,r6,lt0\.b - 30: 04 a0 b9 21 bcnd\.a r4,r6,lt0\.b - 34: 06 00 39 00 br r6 - 38: 06 20 39 00 br\.a r6 - 3c: 0a 00 03 00 brcr PPERROR - 40: 06 00 38 f8 bsr r6,r31 - 44: 06 20 38 f8 bsr\.a r6,r31 - 48: 07 40 30 00 cmnd r7 - 4c: 03 00 3a 29 cmp r3,r4,r5 - 50: 08 00 b7 02 dcachec r8\(r10\) - 54: 08 00 b7 0a dcachef r8\(r10\) - 58: 04 04 b4 41 dld\.b r4\(r6\),r8 - 5c: 04 24 b4 41 dld\.h r4\(r6\),r8 - 60: 04 44 b4 41 dld r4\(r6\),r8 - 64: 04 64 b4 41 dld\.d r4\(r6\),r8 - 68: 04 04 b5 41 dld\.ub r4\(r6\),r8 - 6c: 04 24 b5 41 dld\.uh r4\(r6\),r8 - 70: 04 04 b6 41 dst\.b r4\(r6\),r8 - 74: 04 24 b6 41 dst\.h r4\(r6\),r8 - 78: 04 44 b6 41 dst r4\(r6\),r8 - 7c: 04 64 b6 41 dst\.d r4\(r6\),r8 - 80: 05 20 30 08 etrap r5 - 84: e3 47 71 31 exts r3,31,r5,r6 - 88: c2 07 71 49 extu r2,30,r5,r9 - 8c: 02 00 3e 31 fadd\.sss r2,r4,r6 - 90: 02 02 3e 31 fadd\.ssd r2,r4,r6 - 94: 82 02 3e 31 fadd\.sdd r2,r4,r6 - 98: 22 02 3e 31 fadd\.dsd r2,r4,r6 - 9c: a2 02 3e 31 fadd\.ddd r2,r4,r6 - a0: 04 a0 be 41 fcmp\.ss r4,r6,r8 - a4: 84 a0 be 41 fcmp\.sd r4,r6,r8 - a8: 24 a0 be 41 fcmp\.ds r4,r6,r8 - ac: a4 a0 be 41 fcmp\.dd r4,r6,r8 - b0: 02 60 3e 31 fdiv\.sss r2,r4,r6 - b4: 02 62 3e 31 fdiv\.ssd r2,r4,r6 - b8: 82 62 3e 31 fdiv\.sdd r2,r4,r6 - bc: 22 62 3e 31 fdiv\.dsd r2,r4,r6 - c0: a2 62 3e 31 fdiv\.ddd r2,r4,r6 - c4: 02 40 3e 31 fmpy\.sss r2,r4,r6 - c8: 02 42 3e 31 fmpy\.ssd r2,r4,r6 - cc: 82 42 3e 31 fmpy\.sdd r2,r4,r6 - d0: 22 42 3e 31 fmpy\.dsd r2,r4,r6 - d4: a2 42 3e 31 fmpy\.ddd r2,r4,r6 - d8: 42 45 3e 31 fmpy\.iii r2,r4,r6 - dc: e2 47 3e 31 fmpy\.uuu r2,r4,r6 - e0: 84 81 3e 30 frndm\.ss r4,r6 - e4: 84 83 3e 30 frndm\.sd r4,r6 - e8: 84 85 3e 30 frndm\.si r4,r6 - ec: 84 87 3e 30 frndm\.su r4,r6 - f0: a2 81 3e 40 frndm\.ds r2,r8 - f4: a2 83 3e 40 frndm\.dd r2,r8 - f8: a2 85 3e 40 frndm\.di r2,r8 - fc: a2 87 3e 40 frndm\.du r2,r8 - 100: c4 81 3e 30 frndm\.is r4,r6 - 104: c4 83 3e 30 frndm\.id r4,r6 - 108: e2 81 3e 40 frndm\.us r2,r8 - 10c: e2 83 3e 40 frndm\.ud r2,r8 - 110: 04 80 3e 30 frndn\.ss r4,r6 - 114: 04 82 3e 30 frndn\.sd r4,r6 - 118: 04 84 3e 30 frndn\.si r4,r6 - 11c: 04 86 3e 30 frndn\.su r4,r6 - 120: 22 80 3e 40 frndn\.ds r2,r8 - 124: 22 82 3e 40 frndn\.dd r2,r8 - 128: 22 84 3e 40 frndn\.di r2,r8 - 12c: 22 86 3e 40 frndn\.du r2,r8 - 130: 44 80 3e 30 frndn\.is r4,r6 - 134: 44 82 3e 30 frndn\.id r4,r6 - 138: 62 80 3e 40 frndn\.us r2,r8 - 13c: 62 82 3e 40 frndn\.ud r2,r8 - 140: 04 81 3e 30 frndp\.ss r4,r6 - 144: 04 83 3e 30 frndp\.sd r4,r6 - 148: 04 85 3e 30 frndp\.si r4,r6 - 14c: 04 87 3e 30 frndp\.su r4,r6 - 150: 22 81 3e 40 frndp\.ds r2,r8 - 154: 22 83 3e 40 frndp\.dd r2,r8 - 158: 22 85 3e 40 frndp\.di r2,r8 - 15c: 22 87 3e 40 frndp\.du r2,r8 - 160: 44 81 3e 30 frndp\.is r4,r6 - 164: 44 83 3e 30 frndp\.id r4,r6 - 168: 62 81 3e 40 frndp\.us r2,r8 - 16c: 62 83 3e 40 frndp\.ud r2,r8 - 170: 84 80 3e 30 frndz\.ss r4,r6 - 174: 84 82 3e 30 frndz\.sd r4,r6 - 178: 84 84 3e 30 frndz\.si r4,r6 - 17c: 84 86 3e 30 frndz\.su r4,r6 - 180: a2 80 3e 40 frndz\.ds r2,r8 - 184: a2 82 3e 40 frndz\.dd r2,r8 - 188: a2 84 3e 40 frndz\.di r2,r8 - 18c: a2 86 3e 40 frndz\.du r2,r8 - 190: c4 80 3e 30 frndz\.is r4,r6 - 194: c4 82 3e 30 frndz\.id r4,r6 - 198: e2 80 3e 40 frndz\.us r2,r8 - 19c: e2 82 3e 40 frndz\.ud r2,r8 - 1a0: 06 e0 3e 40 fsqrt\.ss r6,r8 - 1a4: 06 e2 3e 40 fsqrt\.sd r6,r8 - 1a8: 26 e2 3e 40 fsqrt\.dd r6,r8 - 1ac: 02 20 3e 31 fsub\.sss r2,r4,r6 - 1b0: 02 22 3e 31 fsub\.ssd r2,r4,r6 - 1b4: 82 22 3e 31 fsub\.sdd r2,r4,r6 - 1b8: 22 22 3e 31 fsub\.dsd r2,r4,r6 - 1bc: a2 22 3e 31 fsub\.ddd r2,r4,r6 - 1c0: e4 e3 31 52 ins r4,31,r8,r10 - 1c4: 04 80 b8 41 jsr r4\(r6\),r8 - 1c8: 04 a0 b8 41 jsr\.a r4\(r6\),r8 - 1cc: 04 00 b4 41 ld\.b r4\(r6\),r8 - 1d0: 04 20 b4 41 ld\.h r4\(r6\),r8 - 1d4: 04 40 b4 41 ld r4\(r6\),r8 - 1d8: 04 60 b4 41 ld\.d r4\(r6\),r8 - 1dc: 04 00 b5 41 ld\.ub r4\(r6\),r8 - 1e0: 04 20 b5 41 ld\.uh r4\(r6\),r8 - 1e4: 00 00 ff 41 lmo r7,r8 - 1e8: 01 e0 b2 18 or\.tt r1,r2,r3 - 1ec: 01 e0 b2 18 or\.tt r1,r2,r3 - 1f0: 01 c0 b3 18 or\.ff r1,r2,r3 - 1f4: 01 a0 b3 18 or\.ft r1,r2,r3 - 1f8: 01 60 b3 18 or\.tf r1,r2,r3 - 1fc: 06 80 30 20 rdcr r6,r4 - 200: 00 20 3f 29 rmo r4,r5 - 204: e2 03 31 52 rotl r2,31,r8,r10 - 208: e8 07 b1 30 extu r8,31,r2,r6 - 20c: e4 c3 b1 30 shl r4,31,r2,r6 - 210: 84 01 71 31 rotl r4,12,r5,r6 - 214: 84 21 71 31 sl\.dm r4,12,r5,r6 - 218: 84 41 71 31 sl\.ds r4,12,r5,r6 - 21c: 84 61 71 31 sl\.ez r4,12,r5,r6 - 220: 84 81 71 31 sl\.em r4,12,r5,r6 - 224: 84 a1 71 31 sl\.es r4,12,r5,r6 - 228: 84 c1 71 31 shl r4,12,r5,r6 - 22c: 84 e1 71 31 ins r4,12,r5,r6 - 230: 84 09 71 31 sli\.dz r4,12,r5,r6 - 234: 84 29 71 31 sli\.dm r4,12,r5,r6 - 238: 84 49 71 31 sli\.ds r4,12,r5,r6 - 23c: 84 69 71 31 sli\.ez r4,12,r5,r6 - 240: 84 89 71 31 sli\.em r4,12,r5,r6 - 244: 84 a9 71 31 sli\.es r4,12,r5,r6 - 248: 84 c9 71 31 sli\.iz r4,12,r5,r6 - 24c: 84 e9 71 31 sli\.im r4,12,r5,r6 - 250: 84 05 71 31 extu r4,12,r5,r6 - 254: 84 25 71 31 sr\.dm r4,12,r5,r6 - 258: 84 45 71 31 exts r4,12,r5,r6 - 25c: 84 65 71 31 srl r4,12,r5,r6 - 260: 84 85 71 31 sr\.em r4,12,r5,r6 - 264: 84 a5 71 31 sra r4,12,r5,r6 - 268: 84 c5 71 31 sr\.iz r4,12,r5,r6 - 26c: 84 e5 71 31 sr\.im r4,12,r5,r6 - 270: 04 a4 b1 41 sra r4,0,r6,r8 - 274: 84 0d 71 31 sri\.dz r4,12,r5,r6 - 278: 84 2d 71 31 sri\.dm r4,12,r5,r6 - 27c: 84 4d 71 31 sri\.ds r4,12,r5,r6 - 280: 84 6d 71 31 sri\.ez r4,12,r5,r6 - 284: 84 8d 71 31 sri\.em r4,12,r5,r6 - 288: 84 ad 71 31 sri\.es r4,12,r5,r6 - 28c: 84 cd 71 31 sri\.iz r4,12,r5,r6 - 290: 84 ed 71 31 sri\.im r4,12,r5,r6 - 294: 04 64 b1 41 srl r4,0,r6,r8 - 298: 04 00 b6 41 st\.b r4\(r6\),r8 - 29c: 04 20 b6 41 st\.h r4\(r6\),r8 - 2a0: 04 40 b6 41 st r4\(r6\),r8 - 2a4: 04 60 b6 41 st\.d r4\(r6\),r8 - 2a8: 07 40 3b 4a sub r7,r8,r9 - 2ac: 07 60 3b 4a subu r7,r8,r9 - 2b0: 08 a0 b0 21 swcr r8,r6,r4 - 2b4: 0a 20 30 00 trap r10 - 2b8: 02 00 3c 01 vadd\.ss r2,r4,r4 - 2bc: 82 00 bc 01 vadd\.sd r2,r6,r6 - 2c0: a2 00 bc 02 vadd\.dd r2,r10,r10 - 2c4: 06 a0 70 01 wrcr r6,r5 - 2c8: 05 20 b3 39 xnor r5,r6,r7 - 2cc: 07 c0 32 4a xor r7,r8,r9 + 0: 03 00 3b 29.* + 4: 03 20 3b 29.* + 8: 05 20 32 11.* + c: 05 20 32 11.* + 10: 0a 00 33 73.* + 14: 0a 80 32 73.* + 18: 0a 40 32 73.* + 1c: 0a 40 39 1a.* + 20: 0a 60 39 fa.* + 24: 0a 00 39 22.* + 28: 0a 20 39 2a.* + 2c: 04 80 b9 21.* + 30: 04 a0 b9 21.* + 34: 06 00 39 00.* + 38: 06 20 39 00.* + 3c: 0a 00 03 00.* + 40: 06 00 38 f8.* + 44: 06 20 38 f8.* + 48: 07 40 30 00.* + 4c: 03 00 3a 29.* + 50: 08 00 b7 02.* + 54: 08 00 b7 0a.* + 58: 04 04 b4 41.* + 5c: 04 24 b4 41.* + 60: 04 44 b4 41.* + 64: 04 64 b4 41.* + 68: 04 04 b5 41.* + 6c: 04 24 b5 41.* + 70: 04 04 b6 41.* + 74: 04 24 b6 41.* + 78: 04 44 b6 41.* + 7c: 04 64 b6 41.* + 80: 05 20 30 08.* + 84: e3 47 71 31.* + 88: c2 07 71 49.* + 8c: 02 00 3e 31.* + 90: 02 02 3e 31.* + 94: 82 02 3e 31.* + 98: 22 02 3e 31.* + 9c: a2 02 3e 31.* + a0: 04 a0 be 41.* + a4: 84 a0 be 41.* + a8: 24 a0 be 41.* + ac: a4 a0 be 41.* + b0: 02 60 3e 31.* + b4: 02 62 3e 31.* + b8: 82 62 3e 31.* + bc: 22 62 3e 31.* + c0: a2 62 3e 31.* + c4: 02 40 3e 31.* + c8: 02 42 3e 31.* + cc: 82 42 3e 31.* + d0: 22 42 3e 31.* + d4: a2 42 3e 31.* + d8: 42 45 3e 31.* + dc: e2 47 3e 31.* + e0: 84 81 3e 30.* + e4: 84 83 3e 30.* + e8: 84 85 3e 30.* + ec: 84 87 3e 30.* + f0: a2 81 3e 40.* + f4: a2 83 3e 40.* + f8: a2 85 3e 40.* + fc: a2 87 3e 40.* + 100: c4 81 3e 30.* + 104: c4 83 3e 30.* + 108: e2 81 3e 40.* + 10c: e2 83 3e 40.* + 110: 04 80 3e 30.* + 114: 04 82 3e 30.* + 118: 04 84 3e 30.* + 11c: 04 86 3e 30.* + 120: 22 80 3e 40.* + 124: 22 82 3e 40.* + 128: 22 84 3e 40.* + 12c: 22 86 3e 40.* + 130: 44 80 3e 30.* + 134: 44 82 3e 30.* + 138: 62 80 3e 40.* + 13c: 62 82 3e 40.* + 140: 04 81 3e 30.* + 144: 04 83 3e 30.* + 148: 04 85 3e 30.* + 14c: 04 87 3e 30.* + 150: 22 81 3e 40.* + 154: 22 83 3e 40.* + 158: 22 85 3e 40.* + 15c: 22 87 3e 40.* + 160: 44 81 3e 30.* + 164: 44 83 3e 30.* + 168: 62 81 3e 40.* + 16c: 62 83 3e 40.* + 170: 84 80 3e 30.* + 174: 84 82 3e 30.* + 178: 84 84 3e 30.* + 17c: 84 86 3e 30.* + 180: a2 80 3e 40.* + 184: a2 82 3e 40.* + 188: a2 84 3e 40.* + 18c: a2 86 3e 40.* + 190: c4 80 3e 30.* + 194: c4 82 3e 30.* + 198: e2 80 3e 40.* + 19c: e2 82 3e 40.* + 1a0: 06 e0 3e 40.* + 1a4: 06 e2 3e 40.* + 1a8: 26 e2 3e 40.* + 1ac: 02 20 3e 31.* + 1b0: 02 22 3e 31.* + 1b4: 82 22 3e 31.* + 1b8: 22 22 3e 31.* + 1bc: a2 22 3e 31.* + 1c0: e4 e3 31 52.* + 1c4: 04 80 b8 41.* + 1c8: 04 a0 b8 41.* + 1cc: 04 00 b4 41.* + 1d0: 04 20 b4 41.* + 1d4: 04 40 b4 41.* + 1d8: 04 60 b4 41.* + 1dc: 04 00 b5 41.* + 1e0: 04 20 b5 41.* + 1e4: 00 00 ff 41.* + 1e8: 01 e0 b2 18.* + 1ec: 01 e0 b2 18.* + 1f0: 01 c0 b3 18.* + 1f4: 01 a0 b3 18.* + 1f8: 01 60 b3 18.* + 1fc: 06 80 30 20.* + 200: 00 20 3f 29.* + 204: e2 03 31 52.* + 208: e8 07 b1 30.* + 20c: e4 c3 b1 30.* + 210: 84 01 71 31.* + 214: 84 21 71 31.* + 218: 84 41 71 31.* + 21c: 84 61 71 31.* + 220: 84 81 71 31.* + 224: 84 a1 71 31.* + 228: 84 c1 71 31.* + 22c: 84 e1 71 31.* + 230: 84 09 71 31.* + 234: 84 29 71 31.* + 238: 84 49 71 31.* + 23c: 84 69 71 31.* + 240: 84 89 71 31.* + 244: 84 a9 71 31.* + 248: 84 c9 71 31.* + 24c: 84 e9 71 31.* + 250: 84 05 71 31.* + 254: 84 25 71 31.* + 258: 84 45 71 31.* + 25c: 84 65 71 31.* + 260: 84 85 71 31.* + 264: 84 a5 71 31.* + 268: 84 c5 71 31.* + 26c: 84 e5 71 31.* + 270: 04 a4 b1 41.* + 274: 84 0d 71 31.* + 278: 84 2d 71 31.* + 27c: 84 4d 71 31.* + 280: 84 6d 71 31.* + 284: 84 8d 71 31.* + 288: 84 ad 71 31.* + 28c: 84 cd 71 31.* + 290: 84 ed 71 31.* + 294: 04 64 b1 41.* + 298: 04 00 b6 41.* + 29c: 04 20 b6 41.* + 2a0: 04 40 b6 41.* + 2a4: 04 60 b6 41.* + 2a8: 07 40 3b 4a.* + 2ac: 07 60 3b 4a.* + 2b0: 08 a0 b0 21.* + 2b4: 0a 20 30 00.* + 2b8: 02 00 3c 01.* + 2bc: 82 00 bc 01.* + 2c0: a2 00 bc 02.* + 2c4: 06 a0 70 01.* + 2c8: 05 20 b3 39.* + 2cc: 07 c0 32 4a.* diff --git a/gas/testsuite/gas/tic80/relocs1.c b/gas/testsuite/gas/tic80/relocs1.c new file mode 100644 index 00000000000..6af04b1100a --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs1.c @@ -0,0 +1,28 @@ +extern int xfunc (int y); + +static int sfunc (int y) +{ + xfunc (y); +} + +int gfunc (int y) +{ + sfunc (y); +} + +int branches (int y) +{ + int z; + + for (z = y; z < y + 10; z++) + { + if (z & 0x1) + { + gfunc (z); + } + else + { + xfunc (z); + } + } +} diff --git a/gas/testsuite/gas/tic80/relocs1.d b/gas/testsuite/gas/tic80/relocs1.d index 71794e18089..57930a9b3d4 100644 --- a/gas/testsuite/gas/tic80/relocs1.d +++ b/gas/testsuite/gas/tic80/relocs1.d @@ -1,64 +1,60 @@ -#objdump: -dr -#name: TIc80 simple relocs, global/local funcs & branches +#objdump: -d +#name: TIc80 simple relocs, global/local funcs & branches (code) .*: +file format .*tic80.* Disassembly of section .text: 00000000 <_sfunc>: - 0: f0 ff 6c 08 addu -16,r1,r1 - 4: 0c 00 59 f8 st 12\(r1\),r31 - 8: 00 00 59 10 st 0\(r1\),r2 - c: 00 90 38 f8 jsr 0 <_sfunc>\(r0\),r31 - 10: 00 00 00 00 - 10: 32 _xfunc - 14: 00 00 51 10 ld 0\(r1\),r2 - 18: 0c 00 51 f8 ld 12\(r1\),r31 - 1c: 1f 80 38 00 jsr r31\(r0\),r0 - 20: 10 80 6c 08 addu 16,r1,r1 + 0: f0 ff 6c 08.* + 4: 0c 00 59 f8.* + 8: 00 00 59 10.* + c: 00 90 38 f8.* + 10: 00 00 00 00.* + 14: 00 00 51 10.* + 18: 0c 00 51 f8.* + 1c: 1f 80 38 00.* + 20: 10 80 6c 08.* 00000024 <_gfunc>: - 24: f0 ff 6c 08 addu -16,r1,r1 - 28: 0c 00 59 f8 st 12\(r1\),r31 - 2c: 00 00 59 10 st 0\(r1\),r2 - 30: 00 90 38 f8 jsr 0 <_sfunc>\(r0\),r31 - 34: 00 00 00 00 - 34: 32 *ABS* - 38: 00 00 51 10 ld 0\(r1\),r2 - 3c: 0c 00 51 f8 ld 12\(r1\),r31 - 40: 1f 80 38 00 jsr r31\(r0\),r0 - 44: 10 80 6c 08 addu 16,r1,r1 + 24: f0 ff 6c 08.* + 28: 0c 00 59 f8.* + 2c: 00 00 59 10.* + 30: 00 90 38 f8.* + 34: 00 00 00 00.* + 38: 00 00 51 10.* + 3c: 0c 00 51 f8.* + 40: 1f 80 38 00.* + 44: 10 80 6c 08.* 00000048 <_branches>: - 48: f0 ff 6c 08 addu -16,r1,r1 - 4c: 0c 00 59 f8 st 12\(r1\),r31 - 50: 00 00 59 10 st 0\(r1\),r2 - 54: 00 00 51 10 ld 0\(r1\),r2 - 58: 04 00 59 10 st 4\(r1\),r2 - 5c: 00 00 51 10 ld 0\(r1\),r2 - 60: 04 00 51 18 ld 4\(r1\),r3 - 64: 0a 80 ac 10 addu 10,r2,r2 - 68: 03 00 ba 10 cmp r3,r2,r2 - 6c: 12 80 a5 30 bbo\.a b4 <_branches+6c>,r2,ge\.f - 70: 04 00 51 10 ld 4\(r1\),r2 - 74: 05 80 a4 f8 bbz\.a 88 <_branches+40>,r2,eq\.b - 78: 00 90 38 f8 jsr 24 <_gfunc>\(r0\),r31 - 7c: 24 00 00 00 - 7c: 32 *ABS* - 80: 04 00 51 10 ld 4\(r1\),r2 - 84: 04 80 24 00 br\.a 94 <_branches+4c> - 88: 00 90 38 f8 jsr 0 <_sfunc>\(r0\),r31 - 8c: 00 00 00 00 - 8c: 32 _xfunc - 90: 04 00 51 10 ld 4\(r1\),r2 - 94: 04 00 51 10 ld 4\(r1\),r2 - 98: 01 80 ac 10 addu 1,r2,r2 - 9c: 04 00 59 10 st 4\(r1\),r2 - a0: 00 00 51 18 ld 0\(r1\),r3 - a4: 04 00 51 10 ld 4\(r1\),r2 - a8: 0a 80 ec 18 addu 10,r3,r3 - ac: 02 00 fa 10 cmp r2,r3,r2 - b0: f0 ff a5 38 bbo\.a 70 <_branches+28>,r2,lt\.f - b4: 0c 00 51 f8 ld 12\(r1\),r31 - b8: 1f 80 38 00 jsr r31\(r0\),r0 - bc: 10 80 6c 08 addu 16,r1,r1 + 48: f0 ff 6c 08.* + 4c: 0c 00 59 f8.* + 50: 00 00 59 10.* + 54: 00 00 51 10.* + 58: 04 00 59 10.* + 5c: 00 00 51 10.* + 60: 04 00 51 18.* + 64: 0a 80 ac 10.* + 68: 03 00 ba 10.* + 6c: 12 80 a5 30.* + 70: 04 00 51 10.* + 74: 05 80 a4 f8.* + 78: 00 90 38 f8.* + 7c: 24 00 00 00.* + 80: 04 00 51 10.* + 84: 04 80 24 00.* + 88: 00 90 38 f8.* + 8c: 00 00 00 00.* + 90: 04 00 51 10.* + 94: 04 00 51 10.* + 98: 01 80 ac 10.* + 9c: 04 00 59 10.* + a0: 00 00 51 18.* + a4: 04 00 51 10.* + a8: 0a 80 ec 18.* + ac: 02 00 fa 10.* + b0: f0 ff a5 38.* + b4: 0c 00 51 f8.* + b8: 1f 80 38 00.* + bc: 10 80 6c 08.* diff --git a/gas/testsuite/gas/tic80/relocs1b.d b/gas/testsuite/gas/tic80/relocs1b.d new file mode 100644 index 00000000000..6b78da62b27 --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs1b.d @@ -0,0 +1,12 @@ +#objdump: -r +#source: relocs1.s +#name: TIc80 simple relocs, global/local funcs & branches (relocs) + +.*: +file format .*tic80.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000010 32 _xfunc +00000034 32 *ABS* +0000007c 32 *ABS* +0000008c 32 _xfunc diff --git a/gas/testsuite/gas/tic80/relocs2.c b/gas/testsuite/gas/tic80/relocs2.c new file mode 100644 index 00000000000..3f1120c21bd --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs2.c @@ -0,0 +1,41 @@ +extern char x_char; +extern short x_short; +static int x_int; +extern long x_long; +extern float x_float; +extern double x_double; +extern char *x_char_p; + +static char s_char; +static short s_short; +static int s_int; +static long s_long; +static float s_float; +static double s_double; +static char *s_char_p; + +char g_char; +short g_short; +int g_int; +long g_long; +float g_float; +double g_double; +char *g_char_p; + +main () +{ + x_char = s_char; + g_char = x_char; + x_short = s_short; + g_short = x_short; + x_int = s_int; + g_int = x_int; + x_long = s_long; + g_long = x_long; + x_float = s_float; + g_float = x_float; + x_double = s_double; + g_double = x_double; + x_char_p = s_char_p; + g_char_p = x_char_p; +} diff --git a/gas/testsuite/gas/tic80/relocs2.d b/gas/testsuite/gas/tic80/relocs2.d new file mode 100644 index 00000000000..4c19039b87d --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs2.d @@ -0,0 +1,65 @@ +#objdump: -d +#name: TIc80 simple relocs, static and global variables (code) + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <_main>: + 0: 00 10 34 10.* + 4: 1c 00 00 00 + 8: 00 10 36 10.* + c: 00 00 00 00 + 10: 00 10 34 10.* + 14: 00 00 00 00 + 18: 00 10 36 10.* + 1c: 14 00 00 00 + 20: 00 30 34 10.* + 24: 3c 00 00 00 + 28: 00 30 36 10.* + 2c: 00 00 00 00 + 30: 00 30 34 10.* + 34: 00 00 00 00 + 38: 00 30 36 10.* + 3c: 34 00 00 00 + 40: 00 50 34 10.* + 44: 20 00 00 00 + 48: 00 50 36 10.* + 4c: 40 00 00 00 + 50: 00 50 34 10.* + 54: 40 00 00 00 + 58: 00 50 36 10.* + 5c: 18 00 00 00 + 60: 00 50 34 10.* + 64: 10 00 00 00 + 68: 00 50 36 10.* + 6c: 00 00 00 00 + 70: 00 50 34 10.* + 74: 00 00 00 00 + 78: 00 50 36 10.* + 7c: 04 00 00 00 + 80: 00 50 34 10.* + 84: 30 00 00 00 + 88: 00 50 36 10.* + 8c: 00 00 00 00 + 90: 00 50 34 10.* + 94: 00 00 00 00 + 98: 00 50 36 10.* + 9c: 38 00 00 00 + a0: 00 70 34 10.* + a4: 08 00 00 00 + a8: 00 70 36 10.* + ac: 00 00 00 00 + b0: 00 70 34 10.* + b4: 00 00 00 00 + b8: 00 70 36 10.* + bc: 28 00 00 00 + c0: 00 50 34 10.* + c4: 44 00 00 00 + c8: 00 50 36 10.* + cc: 00 00 00 00 + d0: 00 50 34 10.* + d4: 00 00 00 00 + d8: 00 50 36 10.* + dc: 00 00 00 00 + e0: 1f a0 38 00.* diff --git a/gas/testsuite/gas/tic80/relocs2.lst b/gas/testsuite/gas/tic80/relocs2.lst new file mode 100644 index 00000000000..0690a8ce843 --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs2.lst @@ -0,0 +1,112 @@ +MVP MP Macro Assembler Version 1.13 Sun Feb 23 12:16:32 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +relocs2.s PAGE 1 + + 1 ;; This is the hand hacked output of the TI C compiler for a simple + 2 ;; test program that contains static, global, and extern data variables. + 3 + 4 .file "relocs2.s" + 5 .global _x_char + 6 .global _x_short + 7 .global _x_long + 8 .global _x_float + 9 .global _x_double + 10 .global _x_char_p + 11 .global _g_char + 12 .global _g_short + 13 .global _g_int + 14 .global _g_long + 15 .global _g_float + 16 .global _g_double + 17 .global _g_char_p + 18 .global _main + 19 + 20 00000000 _main: + 21 00000000 10341000 ld.b _s_char+0(r0),r2 + 00000004 0000001C + 22 00000008 10361000 st.b _x_char+0(r0),r2 + 0000000C 00000000 + 23 00000010 10341000 ld.b _x_char+0(r0),r2 + 00000014 00000000 + 24 00000018 10361000 st.b _g_char+0(r0),r2 + 0000001C 00000014 + 25 00000020 10343000 ld.h _s_short+0(r0),r2 + 00000024 0000003C + 26 00000028 10363000 st.h _x_short+0(r0),r2 + 0000002C 00000000 + 27 00000030 10343000 ld.h _x_short+0(r0),r2 + 00000034 00000000 + 28 00000038 10363000 st.h _g_short+0(r0),r2 + 0000003C 00000034 + 29 00000040 10345000 ld _s_int+0(r0),r2 + 00000044 00000020 + 30 00000048 10365000 st _x_int+0(r0),r2 + 0000004C 00000040 + 31 00000050 10345000 ld _x_int+0(r0),r2 + 00000054 00000040 + 32 00000058 10365000 st _g_int+0(r0),r2 + 0000005C 00000018 + 33 00000060 10345000 ld _s_long+0(r0),r2 + 00000064 00000010 + 34 00000068 10365000 st _x_long+0(r0),r2 + 0000006C 00000000 + 35 00000070 10345000 ld _x_long+0(r0),r2 + 00000074 00000000 + 36 00000078 10365000 st _g_long+0(r0),r2 + 0000007C 00000004 + 37 00000080 10345000 ld _s_float+0(r0),r2 + 00000084 00000030 + 38 00000088 10365000 st _x_float+0(r0),r2 + MVP MP Macro Assembler Version 1.13 Sun Feb 23 12:16:32 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +relocs2.s PAGE 2 + + 0000008C 00000000 + 39 00000090 10345000 ld _x_float+0(r0),r2 + 00000094 00000000 + 40 00000098 10365000 st _g_float+0(r0),r2 + 0000009C 00000038 + 41 000000A0 10347000 ld.d _s_double+0(r0),r2 + 000000A4 00000008 + 42 000000A8 10367000 st.d _x_double+0(r0),r2 + 000000AC 00000000 + 43 000000B0 10347000 ld.d _x_double+0(r0),r2 + 000000B4 00000000 + 44 000000B8 10367000 st.d _g_double+0(r0),r2 + 000000BC 00000028 + 45 000000C0 10345000 ld _s_char_p+0(r0),r2 + 000000C4 00000044 + 46 000000C8 10365000 st _x_char_p+0(r0),r2 + 000000CC 00000000 + 47 000000D0 10345000 ld _x_char_p+0(r0),r2 + 000000D4 00000000 + 48 000000D8 10365000 st _g_char_p+0(r0),r2 + 000000DC 00000000 + 49 000000E0 0038A01F jsr.a r31(r0),r0 + 50 + 51 .global _g_char_p + 52 00000000 .bss _g_char_p,4,4 + 53 .global _g_long + 54 00000004 .bss _g_long,4,4 + 55 00000008 .bss _s_double,8,8 + 56 00000010 .bss _s_long,4,4 + 57 .global _g_char + 58 00000014 .bss _g_char,1,4 + 59 .global _g_int + 60 00000018 .bss _g_int,4,4 + 61 0000001C .bss _s_char,1,4 + 62 00000020 .bss _s_int,4,4 + 63 .global _g_double + 64 00000028 .bss _g_double,8,8 + 65 00000030 .bss _s_float,4,4 + 66 .global _g_short + 67 00000034 .bss _g_short,2,4 + 68 .global _g_float + 69 00000038 .bss _g_float,4,4 + 70 0000003C .bss _s_short,2,4 + 71 00000040 .bss _x_int,4,4 + 72 00000044 .bss _s_char_p,4,4 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/relocs2.s b/gas/testsuite/gas/tic80/relocs2.s new file mode 100644 index 00000000000..e4257df8656 --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs2.s @@ -0,0 +1,72 @@ +;; This is the hand hacked output of the TI C compiler for a simple +;; test program that contains static, global, and extern data variables. + + .file "relocs2.s" + .global _x_char + .global _x_short + .global _x_long + .global _x_float + .global _x_double + .global _x_char_p + .global _g_char + .global _g_short + .global _g_int + .global _g_long + .global _g_float + .global _g_double + .global _g_char_p + .global _main + +_main: + ld.b _s_char+0(r0),r2 + st.b _x_char+0(r0),r2 + ld.b _x_char+0(r0),r2 + st.b _g_char+0(r0),r2 + ld.h _s_short+0(r0),r2 + st.h _x_short+0(r0),r2 + ld.h _x_short+0(r0),r2 + st.h _g_short+0(r0),r2 + ld _s_int+0(r0),r2 + st _x_int+0(r0),r2 + ld _x_int+0(r0),r2 + st _g_int+0(r0),r2 + ld _s_long+0(r0),r2 + st _x_long+0(r0),r2 + ld _x_long+0(r0),r2 + st _g_long+0(r0),r2 + ld _s_float+0(r0),r2 + st _x_float+0(r0),r2 + ld _x_float+0(r0),r2 + st _g_float+0(r0),r2 + ld.d _s_double+0(r0),r2 + st.d _x_double+0(r0),r2 + ld.d _x_double+0(r0),r2 + st.d _g_double+0(r0),r2 + ld _s_char_p+0(r0),r2 + st _x_char_p+0(r0),r2 + ld _x_char_p+0(r0),r2 + st _g_char_p+0(r0),r2 + jsr.a r31(r0),r0 + + .global _g_char_p + .bss _g_char_p,4,4 + .global _g_long + .bss _g_long,4,4 + .bss _s_double,8,8 + .bss _s_long,4,4 + .global _g_char + .bss _g_char,1,4 + .global _g_int + .bss _g_int,4,4 + .bss _s_char,1,4 + .bss _s_int,4,4 + .global _g_double + .bss _g_double,8,8 + .bss _s_float,4,4 + .global _g_short + .bss _g_short,2,4 + .global _g_float + .bss _g_float,4,4 + .bss _s_short,2,4 + .bss _x_int,4,4 + .bss _s_char_p,4,4 diff --git a/gas/testsuite/gas/tic80/relocs2b.d b/gas/testsuite/gas/tic80/relocs2b.d new file mode 100644 index 00000000000..2fa0b9c8655 --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs2b.d @@ -0,0 +1,38 @@ +#objdump: -r +#source: relocs2.s +#name: TIc80 simple relocs, static and global variables (relocs) + +.*: +file format .*tic80.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000004 32 .bss +0000000c 32 _x_char +00000014 32 _x_char +0000001c 32 .bss +00000024 32 .bss +0000002c 32 _x_short +00000034 32 _x_short +0000003c 32 .bss +00000044 32 .bss +0000004c 32 .bss +00000054 32 .bss +0000005c 32 .bss +00000064 32 .bss +0000006c 32 _x_long +00000074 32 _x_long +0000007c 32 .bss +00000084 32 .bss +0000008c 32 _x_float +00000094 32 _x_float +0000009c 32 .bss +000000a4 32 .bss +000000ac 32 _x_double +000000b4 32 _x_double +000000bc 32 .bss +000000c4 32 .bss +000000cc 32 _x_char_p +000000d4 32 _x_char_p +000000dc 32 .bss + + diff --git a/gas/testsuite/gas/tic80/tic80.exp b/gas/testsuite/gas/tic80/tic80.exp index 5d2ec6e9d2d..dc9f3b4eb10 100644 --- a/gas/testsuite/gas/tic80/tic80.exp +++ b/gas/testsuite/gas/tic80/tic80.exp @@ -10,4 +10,7 @@ if [istarget tic80*-*-*] then { run_dump_test "ccode" run_dump_test "add" run_dump_test "relocs1" + run_dump_test "relocs1b" + run_dump_test "relocs2" + run_dump_test "relocs2b" } -- 2.30.2