From dc4b61823bf386249dc6f503888169a6afe12205 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 4 May 2022 11:29:05 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index f4bbfcc99..537e36fee 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -117,10 +117,9 @@ Vectorisation of the VSX Packed SIMD system makes no sense whatsoever, the sole exceptions potentially being any operations with 128-bit operands such as `vrlq` (Rotate Quad Word) and `xsaddqp` (Scalar Quad-precision Add). -SV effectively *replaces* VSX requiring far less instructions, and provides, -at the very minimum, predication (which VSX was designed without). -Thus all VSX Major Opcodes - all of them - are "unused" and must raise -illegal instruction exceptions in SV Prefix Mode. +SV effectively *replaces* the majority of VSX, requiring far less +instructions, and provides, at the very minimum, predication +(which VSX was designed without). Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to have because they are not only provided by SV, the SV alternatives may -- 2.30.2