From dc4cf11dfc6c0fa7a3e086f16afba0a369fe320a Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 30 Aug 2017 12:07:00 -0700 Subject: [PATCH] intel/fs: Explicitly set EXECUTE_1 where needed Reviewed-by: Iago Toral Quiroga --- src/intel/compiler/brw_fs.cpp | 2 +- src/intel/compiler/brw_fs_generator.cpp | 7 +++++++ src/intel/compiler/brw_fs_nir.cpp | 8 ++++---- src/intel/compiler/brw_fs_visitor.cpp | 7 +++---- 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 40e64a48201..6772c0d5a54 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4298,7 +4298,7 @@ emit_surface_header(const fs_builder &bld, const fs_reg &sample_mask) fs_builder ubld = bld.exec_all().group(8, 0); const fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD); ubld.MOV(dst, brw_imm_d(0)); - ubld.MOV(component(dst, 7), sample_mask); + ubld.group(1, 0).MOV(component(dst, 7), sample_mask); return dst; } diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 46be1c7a497..feb0c49ae1a 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -333,6 +333,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) if (inst->header_size != 0) { brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); brw_set_default_flag_reg(p, 0, 0); @@ -405,11 +406,14 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) /* Check runtime bit to detect if we have to send AA data or not */ brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); + brw_push_insn_state(p); + brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1); brw_AND(p, v1_null_ud, retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD), brw_imm_ud(1<<26)); brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + brw_pop_insn_state(p); int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store; { @@ -956,6 +960,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src /* Explicitly set up the message header by copying g0 to the MRF. */ brw_MOV(p, header_reg, brw_vec8_grf(0, 0)); + brw_set_default_exec_size(p, BRW_EXECUTE_1); if (inst->offset) { /* Set the offset bits in DWord 2. */ brw_MOV(p, get_element_ud(header_reg, 2), @@ -1009,6 +1014,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_exec_size(p, BRW_EXECUTE_1); if (brw_regs_equal(&surface_reg, &sampler_reg)) { brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101)); @@ -1456,6 +1462,7 @@ fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst) brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_MOV(p, flags, dispatch_mask); brw_pop_insn_state(p); } diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 35fae180285..f8970997371 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4201,7 +4201,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr unreachable("not reached"); case nir_intrinsic_vote_any: { - const fs_builder ubld = bld.exec_all(); + const fs_builder ubld = bld.exec_all().group(1, 0); /* The any/all predicates do not consider channel enables. To prevent * dead channels from affecting the result, we initialize the flag with @@ -4233,7 +4233,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } case nir_intrinsic_vote_all: { - const fs_builder ubld = bld.exec_all(); + const fs_builder ubld = bld.exec_all().group(1, 0); /* The any/all predicates do not consider channel enables. To prevent * dead channels from affecting the result, we initialize the flag with @@ -4267,7 +4267,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_vote_eq: { fs_reg value = get_nir_src(instr->src[0]); fs_reg uniformized = bld.emit_uniformize(value); - const fs_builder ubld = bld.exec_all(); + const fs_builder ubld = bld.exec_all().group(1, 0); /* The any/all predicates do not consider channel enables. To prevent * dead channels from affecting the result, we initialize the flag with @@ -4312,7 +4312,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr if (dispatch_width == 32) flag.type = BRW_REGISTER_TYPE_UD; - bld.exec_all().MOV(flag, brw_imm_ud(0u)); + bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u)); bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ); if (instr->dest.ssa.bit_size > 32) { diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 9a19dc25567..481d9c51e7a 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -795,14 +795,13 @@ fs_visitor::emit_barrier() fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); - const fs_builder pbld = bld.exec_all().group(8, 0); - /* Clear the message payload */ - pbld.MOV(payload, brw_imm_ud(0u)); + bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u)); /* Copy the barrier id from r0.2 to the message payload reg.2 */ fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)); - pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask)); + bld.exec_all().group(1, 0).AND(component(payload, 2), r0_2, + brw_imm_ud(barrier_id_mask)); /* Emit a gateway "barrier" message using the payload we set up, followed * by a wait instruction. -- 2.30.2