From dc656d48c2ca36acf6c86f5c38e34710c9fe61d5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Oct 2019 10:38:22 +0200 Subject: [PATCH] targets/sim: switch from shadow_base to io_regions --- litex/boards/targets/arty.py | 4 ++-- litex/boards/targets/genesys2.py | 4 ++-- litex/boards/targets/kc705.py | 4 ++-- litex/boards/targets/kcu105.py | 4 ++-- litex/boards/targets/netv2.py | 4 ++-- litex/boards/targets/nexys4ddr.py | 4 ++-- litex/boards/targets/nexys_video.py | 4 ++-- litex/boards/targets/simple.py | 4 ++-- litex/boards/targets/versa_ecp5.py | 4 ++-- litex/tools/litex_sim.py | 4 ++-- 10 files changed, 20 insertions(+), 20 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 9e4210b2..d8b148a4 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -73,7 +73,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -86,7 +86,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index cfa9f438..9d2ef599 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -65,7 +65,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index ba6aab5c..17d6a108 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -67,7 +67,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 08493966..ba3accd4 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 13137703..9bfa6739 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index e24e6fb9..742e3342 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 73f2565a..06b656b1 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -70,7 +70,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index a1fce670..b615a669 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -31,7 +31,7 @@ class BaseSoC(SoCCore): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 4e673945..bc9eacb1 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -104,7 +104,7 @@ class BaseSoC(SoCSDRAM): class EthernetSoC(BaseSoC): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) @@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index b0238ce1..96fa6637 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -88,7 +88,7 @@ class Platform(SimPlatform): class SimSoC(SoCSDRAM): mem_map = { - "ethmac": 0x30000000, # (shadow @0xb0000000) + "ethmac": 0xb0000000, } mem_map.update(SoCSDRAM.mem_map) @@ -153,7 +153,7 @@ class SimSoC(SoCSDRAM): ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") -- 2.30.2