From dc70987e470d66f584e0ddf606e9f07da994ba75 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 6 Sep 2019 14:44:47 +0100
Subject: [PATCH] arch-arm: ISV bit in DataAbort should check for translation
 stage

According to the ESR spec, the ISV bit is set to 1 only for stage 2
aborts.

Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/faults.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba5151944..c5858c9ae 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1371,7 +1371,7 @@ DataAbort::iss() const
     val  = AbortFault<DataAbort>::iss();
     // ISS is valid if not caused by a stage 1 page table walk, and when taken
     // to AArch64 only when directed to EL2
-    if (!s1ptw && (!to64 || toEL == EL2)) {
+    if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
         val |= isv << 24;
         if (isv) {
             val |= sas << 22;
-- 
2.30.2