From dc76d75756a47325f5233ff684b05d6c0846e86a Mon Sep 17 00:00:00 2001 From: Andrew Bennett Date: Mon, 16 Dec 2013 16:39:47 +0000 Subject: [PATCH] Add support to show the symbolic names of the MIPS CP1 registers. 2013-12-16 Andrew Bennett gas/testsuite/gas/mips/ * mips.exp: Add CP1 register name tests. * cp1-names-mips32.d: New test. * cp1-names-mips32r2.d: New test. * cp1-names-mips64.d: New test. * cp1-names-mips64r2.d: New test. * cp1-names-numeric.d: New test. * cp1-names-r3000.d: New test. * cp1-names-r4000.d: New test. * cp1-names-sb1.d: New test. * cp1-names.s: New test. * micromips-insn32.d: Add the correct symbolic names for the CP1 registers. * micromips-noinsn32.d: Likewise. * micromips-trap.d: Likewise. * micromips.d: Likewise. opcodes/ * mips-dis.c: Add mips_cp1_names pointer. (mips_cp1_names_numeric): New array. (mips_cp1_names_mips3264): New array. (mips_arch_choice): Add cp1_names. (mips_arch_choices): Add relevant cp1 register name array to each of the elements. (set_default_mips_dis_options): Add support for setting up the mips_cp1_names pointer. (parse_mips_dis_option): Add support for the cp1-names command line variable. Also setup the mips_cp1_names pointer. (print_reg): Print out name of the cp1 register. --- gas/testsuite/ChangeLog | 18 +++ gas/testsuite/gas/mips/cp1-names-mips32.d | 74 +++++++++++ gas/testsuite/gas/mips/cp1-names-mips32r2.d | 74 +++++++++++ gas/testsuite/gas/mips/cp1-names-mips64.d | 74 +++++++++++ gas/testsuite/gas/mips/cp1-names-mips64r2.d | 74 +++++++++++ gas/testsuite/gas/mips/cp1-names-numeric.d | 74 +++++++++++ gas/testsuite/gas/mips/cp1-names-r3000.d | 75 +++++++++++ gas/testsuite/gas/mips/cp1-names-r4000.d | 75 +++++++++++ gas/testsuite/gas/mips/cp1-names-sb1.d | 74 +++++++++++ gas/testsuite/gas/mips/cp1-names.s | 77 +++++++++++ gas/testsuite/gas/mips/micromips-insn32.d | 84 ++++++------ gas/testsuite/gas/mips/micromips-noinsn32.d | 84 ++++++------ gas/testsuite/gas/mips/micromips-trap.d | 84 ++++++------ gas/testsuite/gas/mips/micromips.d | 84 ++++++------ gas/testsuite/gas/mips/mips.exp | 12 ++ opcodes/ChangeLog | 14 ++ opcodes/mips-dis.c | 140 ++++++++++++++------ 17 files changed, 984 insertions(+), 207 deletions(-) create mode 100644 gas/testsuite/gas/mips/cp1-names-mips32.d create mode 100644 gas/testsuite/gas/mips/cp1-names-mips32r2.d create mode 100644 gas/testsuite/gas/mips/cp1-names-mips64.d create mode 100644 gas/testsuite/gas/mips/cp1-names-mips64r2.d create mode 100644 gas/testsuite/gas/mips/cp1-names-numeric.d create mode 100644 gas/testsuite/gas/mips/cp1-names-r3000.d create mode 100644 gas/testsuite/gas/mips/cp1-names-r4000.d create mode 100644 gas/testsuite/gas/mips/cp1-names-sb1.d create mode 100644 gas/testsuite/gas/mips/cp1-names.s diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 2c518531733..be612994720 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,21 @@ +2013-12-16 Andrew Bennett + + * gas/mips/mips.exp: Add CP1 register name tests. + * gas/mips/cp1-names-mips32.d: New test. + * gas/mips/cp1-names-mips32r2.d: New test. + * gas/mips/cp1-names-mips64.d: New test. + * gas/mips/cp1-names-mips64r2.d: New test. + * gas/mips/cp1-names-numeric.d: New test. + * gas/mips/cp1-names-r3000.d: New test. + * gas/mips/cp1-names-r4000.d: New test. + * gas/mips/cp1-names-sb1.d: New test. + * gas/mips/cp1-names.s: New test. + * gas/mips/micromips-insn32.d: Add the correct symbolic names for the CP1 + registers. + * gas/mips/micromips-noinsn32.d: Likewise. + * gas/mips/micromips-trap.d: Likewise. + * gas/mips/micromips.d: Likewise. + 2013-12-16 Andrew Bennett * gas/mips/msa.s: Reduced maximum element index range diff --git a/gas/testsuite/gas/mips/cp1-names-mips32.d b/gas/testsuite/gas/mips/cp1-names-mips32.d new file mode 100644 index 00000000000..93d32539b1c --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-mips32.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips32 +#name: MIPS CP1 register disassembly (mips32) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-mips32r2.d b/gas/testsuite/gas/mips/cp1-names-mips32r2.d new file mode 100644 index 00000000000..03d6a1976e5 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-mips32r2.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips32r2 +#name: MIPS CP1 register disassembly (mips32r2) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-mips64.d b/gas/testsuite/gas/mips/cp1-names-mips64.d new file mode 100644 index 00000000000..a7afaf1f3e3 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-mips64.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips64 +#name: MIPS CP1 register disassembly (mips64) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-mips64r2.d b/gas/testsuite/gas/mips/cp1-names-mips64r2.d new file mode 100644 index 00000000000..45bc9d1e506 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-mips64r2.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips64r2 +#name: MIPS CP1 register disassembly (mips64r2) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-numeric.d b/gas/testsuite/gas/mips/cp1-names-numeric.d new file mode 100644 index 00000000000..e0ab3376600 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-numeric.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=numeric +#name: MIPS CP1 register disassembly (numeric) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0 +0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1 +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,\$4 +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,\$25 +0+0068 <[^>]*> 44c0d000 ctc1 \$0,\$26 +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28 +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31 +0+0080 <[^>]*> 44400000 cfc1 \$0,\$0 +0+0084 <[^>]*> 44400800 cfc1 \$0,\$1 +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,\$4 +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,\$25 +0+00e8 <[^>]*> 4440d000 cfc1 \$0,\$26 +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28 +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31 + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-r3000.d b/gas/testsuite/gas/mips/cp1-names-r3000.d new file mode 100644 index 00000000000..25b5bfbc6b5 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-r3000.d @@ -0,0 +1,75 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=r3000 +#name: MIPS CP1 register disassembly (r3000) +#as: -32 -march=r3000 +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0 +0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1 +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,\$4 +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,\$25 +0+0068 <[^>]*> 44c0d000 ctc1 \$0,\$26 +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28 +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31 +0+0080 <[^>]*> 44400000 cfc1 \$0,\$0 +0+0084 <[^>]*> 44400800 cfc1 \$0,\$1 +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,\$4 +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,\$25 +0+00e8 <[^>]*> 4440d000 cfc1 \$0,\$26 +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28 +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31 + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-r4000.d b/gas/testsuite/gas/mips/cp1-names-r4000.d new file mode 100644 index 00000000000..a1030a2a97e --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-r4000.d @@ -0,0 +1,75 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric +#name: MIPS CP1 register disassembly +#as: -32 -march=r4000 +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0 +0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1 +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,\$4 +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,\$25 +0+0068 <[^>]*> 44c0d000 ctc1 \$0,\$26 +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28 +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31 +0+0080 <[^>]*> 44400000 cfc1 \$0,\$0 +0+0084 <[^>]*> 44400800 cfc1 \$0,\$1 +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,\$4 +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,\$25 +0+00e8 <[^>]*> 4440d000 cfc1 \$0,\$26 +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28 +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31 + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names-sb1.d b/gas/testsuite/gas/mips/cp1-names-sb1.d new file mode 100644 index 00000000000..dc4407d8718 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names-sb1.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=sb1 +#name: MIPS CP1 register disassembly (sb1) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/gas/testsuite/gas/mips/cp1-names.s b/gas/testsuite/gas/mips/cp1-names.s new file mode 100644 index 00000000000..7572354d9c0 --- /dev/null +++ b/gas/testsuite/gas/mips/cp1-names.s @@ -0,0 +1,77 @@ +# source file to test objdump's disassembly using various styles of +# CP1 register names. + + .set noreorder + .set noat + + .globl text_label .text +text_label: + + ctc1 $0, $0 + ctc1 $0, $1 + ctc1 $0, $2 + ctc1 $0, $3 + ctc1 $0, $4 + ctc1 $0, $5 + ctc1 $0, $6 + ctc1 $0, $7 + ctc1 $0, $8 + ctc1 $0, $9 + ctc1 $0, $10 + ctc1 $0, $11 + ctc1 $0, $12 + ctc1 $0, $13 + ctc1 $0, $14 + ctc1 $0, $15 + ctc1 $0, $16 + ctc1 $0, $17 + ctc1 $0, $18 + ctc1 $0, $19 + ctc1 $0, $20 + ctc1 $0, $21 + ctc1 $0, $22 + ctc1 $0, $23 + ctc1 $0, $24 + ctc1 $0, $25 + ctc1 $0, $26 + ctc1 $0, $27 + ctc1 $0, $28 + ctc1 $0, $29 + ctc1 $0, $30 + ctc1 $0, $31 + + cfc1 $0, $0 + cfc1 $0, $1 + cfc1 $0, $2 + cfc1 $0, $3 + cfc1 $0, $4 + cfc1 $0, $5 + cfc1 $0, $6 + cfc1 $0, $7 + cfc1 $0, $8 + cfc1 $0, $9 + cfc1 $0, $10 + cfc1 $0, $11 + cfc1 $0, $12 + cfc1 $0, $13 + cfc1 $0, $14 + cfc1 $0, $15 + cfc1 $0, $16 + cfc1 $0, $17 + cfc1 $0, $18 + cfc1 $0, $19 + cfc1 $0, $20 + cfc1 $0, $21 + cfc1 $0, $22 + cfc1 $0, $23 + cfc1 $0, $24 + cfc1 $0, $25 + cfc1 $0, $26 + cfc1 $0, $27 + cfc1 $0, $28 + cfc1 $0, $29 + cfc1 $0, $30 + cfc1 $0, $31 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/micromips-insn32.d b/gas/testsuite/gas/mips/micromips-insn32.d index a28c519585e..c0ff2db98bb 100644 --- a/gas/testsuite/gas/mips/micromips-insn32.d +++ b/gas/testsuite/gas/mips/micromips-insn32.d @@ -5412,11 +5412,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5437,18 +5437,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5469,13 +5469,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5508,11 +5508,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5533,18 +5533,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5565,13 +5565,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6787,11 +6787,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6812,18 +6812,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6844,13 +6844,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/gas/testsuite/gas/mips/micromips-noinsn32.d b/gas/testsuite/gas/mips/micromips-noinsn32.d index 520c9cb3f87..5bbaab1f81e 100644 --- a/gas/testsuite/gas/mips/micromips-noinsn32.d +++ b/gas/testsuite/gas/mips/micromips-noinsn32.d @@ -5391,11 +5391,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5416,18 +5416,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5448,13 +5448,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5487,11 +5487,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5512,18 +5512,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5544,13 +5544,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6766,11 +6766,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6791,18 +6791,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6823,13 +6823,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/gas/testsuite/gas/mips/micromips-trap.d b/gas/testsuite/gas/mips/micromips-trap.d index f1167a0af9a..cfb0979d05f 100644 --- a/gas/testsuite/gas/mips/micromips-trap.d +++ b/gas/testsuite/gas/mips/micromips-trap.d @@ -5397,11 +5397,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5422,18 +5422,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5454,13 +5454,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5493,11 +5493,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5518,18 +5518,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5550,13 +5550,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6757,11 +6757,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6782,18 +6782,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6814,13 +6814,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/gas/testsuite/gas/mips/micromips.d b/gas/testsuite/gas/mips/micromips.d index 4821d0997e9..e26266352b7 100644 --- a/gas/testsuite/gas/mips/micromips.d +++ b/gas/testsuite/gas/mips/micromips.d @@ -5469,11 +5469,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5494,18 +5494,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5526,13 +5526,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5565,11 +5565,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5590,18 +5590,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5622,13 +5622,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6844,11 +6844,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6869,18 +6869,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6901,13 +6901,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index dfc92d95298..ece3a1354c0 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -971,6 +971,18 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "cp0sel-names-mips64r2" run_dump_test "cp0sel-names-sb1" + run_dump_test "cp1-names-numeric" + run_dump_test "cp1-names-r3000" + run_dump_test "cp1-names-r4000" \ + { { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } } + run_dump_test "cp1-names-r4000" \ + { { {name} {(r4400)} } { {objdump} {-M cp0-names=r4400} } } + run_dump_test "cp1-names-mips32" + run_dump_test "cp1-names-mips32r2" + run_dump_test "cp1-names-mips64" + run_dump_test "cp1-names-mips64r2" + run_dump_test "cp1-names-sb1" + run_dump_test "hwr-names-numeric" run_dump_test "hwr-names-mips32r2" run_dump_test "hwr-names-mips64r2" diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9c88d3f3751..9ee7c75b026 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2013-12-16 Andrew Bennett + + * mips-dis.c: Add mips_cp1_names pointer. + (mips_cp1_names_numeric): New array. + (mips_cp1_names_mips3264): New array. + (mips_arch_choice): Add cp1_names. + (mips_arch_choices): Add relevant cp1 register name array to each of + the elements. + (set_default_mips_dis_options): Add support for setting up the + mips_cp1_names pointer. + (parse_mips_dis_option): Add support for the cp1-names command line + variable. Also setup the mips_cp1_names pointer. + (print_reg): Print out name of the cp1 register. + 2013-12-16 Andrew Bennett * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 1929ffcac95..09a2ed1309e 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -115,6 +115,14 @@ static const char * const mips_cp0_names_numeric[32] = "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; +static const char * const mips_cp1_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + static const char * const mips_cp0_names_r3000[32] = { "c0_index", "c0_random", "c0_entrylo", "$3", @@ -175,6 +183,18 @@ static const char * const mips_cp0_names_mips3264[32] = "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; +static const char * const mips_cp1_names_mips3264[32] = +{ + "c1_fir", "c1_ufr", "$2", "$3", + "c1_unfr", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", + "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", + "$20", "$21", "$22", "$23", + "$24", "c1_fccr", "c1_fexr", "$27", + "c1_fenr", "$29", "$30", "c1_fcsr" +}; + static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { { 16, 1, "c0_config1" }, @@ -436,62 +456,88 @@ struct mips_arch_choice const char * const *cp0_names; const struct mips_cp0sel_name *cp0sel_names; unsigned int cp0sel_names_len; + const char * const *cp1_names; const char * const *hwr_names; }; const struct mips_arch_choice mips_arch_choices[] = { { "numeric", 0, 0, 0, 0, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0, - mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, - mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0, - mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0, - mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. Note that MIPS-3D and MDMX are not applicable to MIPS32. (See @@ -502,7 +548,7 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS32, ASE_SMARTMIPS, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2, @@ -510,14 +556,14 @@ const struct mips_arch_choice mips_arch_choices[] = | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), - mips_hwr_names_mips3264r2 }, + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, ISA_MIPS64, ASE_MIPS3D | ASE_MDMX, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, ISA_MIPS64R2, @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] = | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), - mips_hwr_names_mips3264r2 }, + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, ISA_MIPS64 | INSN_SB1, ASE_MIPS3D, mips_cp0_names_sb1, mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, ISA_MIPS64 | INSN_XLR, 0, mips_cp0_names_xlr, mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, /* XLP is mostly like XLR, with the prominent exception it is being MIPS64R2. */ @@ -569,12 +615,13 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS64R2 | INSN_XLR, 0, mips_cp0_names_xlr, mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, }; /* ISA and processor type to disassemble for, and register names to use. @@ -589,6 +636,7 @@ static const char * const *mips_fpr_names; static const char * const *mips_cp0_names; static const struct mips_cp0sel_name *mips_cp0sel_names; static int mips_cp0sel_names_len; +static const char * const *mips_cp1_names; static const char * const *mips_hwr_names; /* Other options */ @@ -694,6 +742,7 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_cp0_names = mips_cp0_names_numeric; mips_cp0sel_names = NULL; mips_cp0sel_names_len = 0; + mips_cp1_names = mips_cp1_names_numeric; mips_hwr_names = mips_hwr_names_numeric; no_aliases = 0; @@ -727,6 +776,7 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_cp0_names = chosen_arch->cp0_names; mips_cp0sel_names = chosen_arch->cp0sel_names; mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_cp1_names = chosen_arch->cp1_names; mips_hwr_names = chosen_arch->hwr_names; } #endif @@ -810,6 +860,15 @@ parse_mips_dis_option (const char *option, unsigned int len) return; } + if (strncmp ("cp1-names", option, optionlen) == 0 + && strlen ("cp1-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + mips_cp1_names = chosen_arch->cp1_names; + return; + } + if (strncmp ("hwr-names", option, optionlen) == 0 && strlen ("hwr-names") == optionlen) { @@ -838,6 +897,7 @@ parse_mips_dis_option (const char *option, unsigned int len) mips_cp0_names = chosen_arch->cp0_names; mips_cp0sel_names = chosen_arch->cp0sel_names; mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_cp1_names = chosen_arch->cp1_names; mips_hwr_names = chosen_arch->hwr_names; } return; @@ -927,6 +987,8 @@ print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, case OP_REG_COPRO: if (opcode->name[strlen (opcode->name) - 1] == '0') info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]); + else if (opcode->name[strlen (opcode->name) - 1] == '1') + info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]); else info->fprintf_func (info->stream, "$%d", regno); break; -- 2.30.2