From dc78ee41a776646bf89aaed741b5f78c82bbd571 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 01:24:20 +0100 Subject: [PATCH] collate fu-enable signals --- src/soc/simple/core.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 54e60864..d25285bf 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -39,19 +39,20 @@ class NonProductionCore(Elaboratable): regs = self.regs fus = self.fus.fus + # enable-signals for each FU, get one bit for each FU (by name) + fu_enable = Signal(len(fus), reset_less=True) + fu_bitdict = {} + for i, funame in enumerate(fus.keys()): + fu_bitdict[funame] = fu_enable[i] + # connect up instructions for funame, fu in fus.items(): fnunit = fu.fnunit.value enable = Signal(name="en_%s" % funame, reset_less=True) - comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit != 0)) + comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool()) with m.If(enable): comb += fu.oper_i.eq_from_execute1(dec2.e) - - # enable-signals for each FU, get one bit for each FU (by name) - fu_enable = Signal(len(fus), reset_less=True) - fu_bitdict = {} - for i, funame in enumerate(fus.keys()): - fu_bitdict[funame] = fu_enable[i] + comb += fu_bitdict[funame].eq(enable) # dictionary of lists of regfile read ports byregfiles_rd = {} -- 2.30.2