From dc79b2d58cb7b93dd4384fa25ed0810a5605d151 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Jul 2021 16:12:14 +0100 Subject: [PATCH] add in extra "vertical" mode into SVP64 setvl --- openpower/isa/simplev.mdwn | 40 ++++++++++--------- openpower/isatables/fields.text | 9 +++-- src/openpower/consts.py | 1 + .../decoder/isa/test_caller_setvl.py | 4 +- src/openpower/sv/trans/svp64.py | 9 +++-- 5 files changed, 36 insertions(+), 27 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 37b39e26..a5182547 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -6,28 +6,32 @@ SVL-Form -* setvl RT, RA, SVi, vs, ms -* setvl. RT, RA, SVi, vs, ms +* setvl RT, RA, SVi, vf, vs, ms +* setvl. RT, RA, SVi, vf, vs, ms Pseudo-code: - VLimm <- SVi + 1 - if vs = 1 then - if _RA != 0 then - VL <- (RA|0)[57:63] - else - VL <- VLimm[1:7] - else - VL <- SVSTATE[7:13] - if ms = 1 then - MVL <- VLimm[1:7] + if (vf & (¬vs) & ¬(ms)) = 1 then + SVSTATE_NEXT(vf) else - MVL <- SVSTATE[0:6] - if VL > MVL then - VL = MVL - SVSTATE[0:6] <- MVL - SVSTATE[7:13] <- VL - RT <- [0]*57 || VL + VLimm <- SVi + 1 + if vs = 1 then + if _RA != 0 then + VL <- (RA|0)[57:63] + else + VL <- VLimm[0:6] + else + VL <- SVSTATE[7:13] + if ms = 1 then + MVL <- VLimm[0:6] + else + MVL <- SVSTATE[0:6] + if VL > MVL then + VL = MVL + SVSTATE[0:6] <- MVL + SVSTATE[7:13] <- VL + RT <- [0]*57 || VL + MSR[6] <- vf Special Registers Altered: diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index bcdcdbd1..2562f843 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -252,8 +252,8 @@ | PO | RT| d1| d0| XO|d2 # 1.6.28 SVL-FORM - |0 |6 |11 |16 |22 |24 |25 |26 |31 | - | PO | RT | RA | SVi |// |vs |ms | XO |Rc | + |0 |6 |11 |16 |23 |24 |25 |26 |31 | + | PO | RT | RA | SVi |vf |vs |ms | XO |Rc | # 1.6.29 SVC-FORM |0 |6 |9 |11 | @@ -758,7 +758,7 @@ two's complement integer which is concatenated on the right with 0b00 and sign-extended to 64 bits. Formats: SVDS - SVi (16:23) + SVi (16:22) Simple-V immediate field for setting VL or MVL Formats: SVL SVRM (21:25) @@ -855,6 +855,9 @@ VRT (6:10) Field used to specify a VR to be used as a target. Formats: DS, VA, VC, VX, X + vf (23) + Field used in Simple-V to specify whether "Vertical" Mode is set + Formats: SVL vs (24) Field used in Simple-V to specify whether VL is to be set Formats: SVL diff --git a/src/openpower/consts.py b/src/openpower/consts.py index 5c60bd97..057bd262 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -90,6 +90,7 @@ class MSRb: SF = 0 # Sixty-Four bit mode HV = 3 # Hypervisor state UND = 5 # Undefined behavior state (see Bk 2, Sect. 3.2.1) + SVF = 6 # SVP64 "Vertical First" mode TSs = 29 # Transactional State (subfield) TSe = 30 # Transactional State (subfield) TM = 31 # Transactional Memory Available diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 0a66dfeb..b6cdc6ed 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -22,7 +22,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) def test_setvl_1(self): - lst = SVP64Asm(["setvl 1, 0, 9, 1, 1", + lst = SVP64Asm(["setvl 1, 0, 9, 0, 1, 1", ]) lst = list(lst) @@ -48,7 +48,7 @@ class DecoderTestCase(FHDLTestCase): # sets VL=2 then adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 - isa = SVP64Asm(["setvl 3, 0, 1, 1, 1", + isa = SVP64Asm(["setvl 3, 0, 1, 0, 1, 1", 'sv.add 1.v, 5.v, 9.v' ]) lst = list(isa) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 1c4c73ad..1c12ea7f 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -186,9 +186,10 @@ class SVP64Asm: fields = list(map(int, fields)) insn |= fields[0] << (31-10) # RT , bits 6-10 insn |= fields[1] << (31-15) # RA , bits 11-15 - insn |= fields[2] << (31-23) # SVi , bits 16-23 - insn |= fields[3] << (31-24) # vs , bit 24 - insn |= fields[4] << (31-25) # ms , bit 25 + insn |= fields[2] << (31-22) # SVi , bits 16-22 + insn |= fields[3] << (31-23) # vf , bit 23 + insn |= fields[4] << (31-24) # vs , bit 24 + insn |= fields[5] << (31-25) # ms , bit 25 insn |= 0b00000 << (31-30) # XO , bits 26..30 if opcode == 'setvl.': insn |= 1 << (31-31) # Rc=1 , bit 31 @@ -950,7 +951,7 @@ if __name__ == '__main__': lst += [ 'sv.stw 5.v, 4(1.v)', 'sv.ld 5.v, 4(1.v)', - 'setvl. 2, 3, 4, 1, 1', + 'setvl. 2, 3, 4, 0, 1, 1', ] lst = [ "sv.stfsu 0.v, 16(4.v)", -- 2.30.2