From dc82fa46038a1107417a304e7582a3d1ed35c8e7 Mon Sep 17 00:00:00 2001
From: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
Date: Fri, 15 Mar 2019 16:12:13 +0100
Subject: [PATCH] Only Imported FPGetOp

---
 a36447fc            |  743 ++++++++++++++
 ca218a65            |  599 +++++++++++
 git diff a36447fc^  |  505 +++++++++
 search for a36447fc | 2363 +++++++++++++++++++++++++++++++++++++++++++
 src/add/fmul.py     |    3 +-
 5 files changed, 4212 insertions(+), 1 deletion(-)
 create mode 100644 a36447fc
 create mode 100644 ca218a65
 create mode 100644 git diff a36447fc^
 create mode 100644 search for a36447fc

diff --git a/a36447fc b/a36447fc
new file mode 100644
index 00000000..90b928af
--- /dev/null
+++ b/a36447fc
@@ -0,0 +1,743 @@
+commit f02c6f4bbf463472d3d68e52bd5ededd3c937f58 (HEAD -> master, origin/master, origin/HEAD)
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 12:37:14 2019 +0000
+
+    add parallel InputGroup unit test
+
+commit b13c8a7a5368a53bedc71e5b8969c721103144c4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 10:59:44 2019 +0000
+
+    rename BufPipe example to ExampleBufPipe
+
+commit a36447fcd4d4f049b7127e1fc02dc1390d05fa75
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:59:07 2019 +0000
+
+    instantiate 2 FPGetOp instances and use them.  a little awkwardly.
+
+commit 092d2d78fa19a5c73863cb89c5d680cbd2afe027
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:33:44 2019 +0000
+
+    update comments
+
+commit 8989cd3452869d43a8a3655acffd3eb3288f5d9a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:22:58 2019 +0000
+
+    remove unnecessary code
+
+commit b90c533476affe63a34292bfe54dde62a105bed8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:47:21 2019 +0000
+
+    add extra comment block explaining pipe stage example
+
+commit 28a8ede4a797a76e83410fb42a9aaa02b44fb2ef
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:37:18 2019 +0000
+
+    inverted busy signal and named it "ready"
+
+commit 0ebc09c0a7b74e4807ccdb60ca0a10cbb605666a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:29:56 2019 +0000
+
+    rename stb to "valid"
+
+commit 0bfbc8ff919f0cd9c7f01b4c711b1b91a53ad480
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:28:18 2019 +0000
+
+    create classes for STB/BUSY, split in from out
+
+commit ca218a65dc9af73965a5c4f105a780ed04b588e0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 00:31:30 2019 +0000
+
+    add use of FPState, not being used yet
+
+commit ce7a1d5c48e987cbfb40236f13b17ffcea55b585
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 13:32:06 2019 +0000
+
+    split pipeline test into 2 functions, one send, one receive
+
+commit 481d00c37b31e7908e624235e6e9c93b12baeebb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 06:33:10 2019 +0000
+
+    got fpdiv up and running again
+
+commit 286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 05:41:02 2019 +0000
+
+    forgot to add submodules
+
+commit 43c53078d577aa33d28ba0eb2af782b7d348a517
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 05:09:36 2019 +0000
+
+    got rounding working again for fmul
+
+commit 892d640f8224e6a52907c6899ab6ab671f5f53af
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:42:53 2019 +0000
+
+    remove extra arg from old roundz function
+
+commit ccd4d65a7bd2985edb5547daf7df623cda5ab9da
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:33:01 2019 +0000
+
+    make a bit of a mess of the unit tests, getting mul up and running again
+    taking a copy (sigh) of the old version of check_case and get_case
+
+commit 9b9732e1c96d085bc9c7b696e7c86dd0c4a4ae49
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:17:28 2019 +0000
+
+    get roundz working again, needed for mul stage
+
+commit 38452d7fb64752a897b26e1da96a27d3a5979a76
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:16:28 2019 +0000
+
+    add new FPNormaliseSingleMod, not tested
+diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
+index 6678a67..00eecc3 100644
+--- a/src/add/example_buf_pipe.py
++++ b/src/add/example_buf_pipe.py
+@@ -12,12 +12,12 @@
+     where data will flow on *every* clock when the conditions are right.
+ 
+     input acceptance conditions are when:
+-        * incoming previous-stage strobe (i_p_stb) is HIGH
+-        * outgoing previous-stage busy   (o_p_busy) is LOW
++        * incoming previous-stage strobe (i.p_valid) is HIGH
++        * outgoing previous-stage ready   (o.p_ready) is LOW
+ 
+     output transmission conditions are when:
+-        * outgoing next-stage strobe (o_n_stb) is HIGH
+-        * outgoing next-stage busy   (i_n_busy) is LOW
++        * outgoing next-stage strobe (o.n_valid) is HIGH
++        * outgoing next-stage ready   (i.n_ready) is LOW
+ 
+     the tricky bit is when the input has valid data and the output is not
+     ready to accept it.  if it wasn't for the clock synchronisation, it
+@@ -33,7 +33,7 @@
+     we now effectively have *two* possible pieces of data to "choose" from:
+     the buffered data, and the incoming data.  the decision as to which
+     to process and output is based on whether we are in "stall" or not.
+-    i.e. when the next stage is no longer busy, the output comes from
++    i.e. when the next stage is no longer ready, the output comes from
+     the buffer if a stall had previously occurred, otherwise it comes
+     direct from processing the input.
+ 
+@@ -69,7 +69,17 @@ class ExampleStage:
+ 
+     def __init__(self):
+         """ i_data can be a DIFFERENT type from everything else
+-            o_data, r_data and result must be of the same type
++            o_data, r_data and result are best of the same type.
++            however this is not strictly necessary.  an intermediate
++            transformation process could hypothetically be applied, however
++            it is result and r_data that definitively need to be of the same
++            (intermediary) type, as it is both result and r_data that
++            are transferred into o_data:
++
++            i_data -> process() -> result --> o_data
++                                     |           ^
++                                     |           |
++                                     +-> r_data -+
+         """
+         self.i_data = Signal(16)
+         self.r_data = Signal(16)
+@@ -83,7 +93,9 @@ class ExampleStage:
+         return self.result.eq(self.i_data + 1)
+ 
+     def update_buffer(self):
+-        """ copies the result into the intermediate register r_data
++        """ copies the result into the intermediate register r_data,
++            which will need to be outputted on a subsequent cycle
++            prior to allowing "normal" operation.
+         """
+         return self.r_data.eq(self.result)
+ 
+@@ -100,88 +112,98 @@ class ExampleStage:
+     def ports(self):
+         return [self.i_data, self.o_data]
+ 
++class IOAckIn:
++
++    def __init__(self):
++        self.p_valid = Signal() # >>in - comes in from PREVIOUS stage
++        self.n_ready = Signal() # in<< - comes in from the NEXT stage
++
++
++class IOAckOut:
++
++    def __init__(self):
++        self.n_valid = Signal() # out>> - goes out to the NEXT stage
++        self.p_ready = Signal() # <<out - goes out to the PREVIOUS stage
++
+ 
+ class BufferedPipeline:
+     """ buffered pipeline stage
+ 
+-        stage-1   i_p_stb  >>in   stage   o_n_stb  out>>   stage+1
+-        stage-1   o_p_busy <<out  stage   i_n_busy <<in    stage+1
+-        stage-1   i_data   >>in   stage   o_data   out>>   stage+1
++        stage-1   i.p_valid >>in   stage   o.n_valid out>>   stage+1
++        stage-1   o.p_ready <<out  stage   i.n_ready <<in    stage+1
++        stage-1   i_data    >>in   stage   o_data    out>>   stage+1
+                               |             |
+                               +------->  process
+                               |             |
+                               +-- r_data ---+
+     """
+     def __init__(self):
+-        # input: strobe comes in from previous stage, busy comes in from next
+-        #self.i_p_rst = Signal()    # >>in - comes in from PREVIOUS stage
+-        self.i_p_stb = Signal()    # >>in - comes in from PREVIOUS stage
+-        self.i_n_busy = Signal()   # in<< - comes in from the NEXT stage
++        # input: strobe comes in from previous stage, ready comes in from next
++        self.i = IOAckIn()
++        #self.i.p_valid = Signal()    # >>in - comes in from PREVIOUS stage
++        #self.i.n_ready = Signal()   # in<< - comes in from the NEXT stage
+ 
+-        # output: strobe goes out to next stage, busy comes in from previous
+-        self.o_n_stb = Signal()    # out>> - goes out to the NEXT stage
+-        self.o_p_busy = Signal()   # <<out - goes out to the PREVIOUS stage
++        # output: strobe goes out to next stage, ready comes in from previous
++        self.o = IOAckOut()
++        #self.o.n_valid = Signal()    # out>> - goes out to the NEXT stage
++        #self.o.p_ready = Signal()   # <<out - goes out to the PREVIOUS stage
+ 
+     def elaborate(self, platform):
+         m = Module()
+ 
+         # establish some combinatorial temporaries
+-        o_p_busyn = Signal(reset_less=True)
+-        o_n_stbn = Signal(reset_less=True)
+-        i_n_busyn = Signal(reset_less=True)
+-        i_p_stb_o_p_busyn = Signal(reset_less=True)
+-        m.d.comb += [i_n_busyn.eq(~self.i_n_busy),
+-                     o_n_stbn.eq(~self.o_n_stb),
+-                     o_p_busyn.eq(~self.o_p_busy),
+-                     i_p_stb_o_p_busyn.eq(self.i_p_stb & o_p_busyn),
++        o_n_validn = Signal(reset_less=True)
++        i_p_valid_o_p_ready = Signal(reset_less=True)
++        m.d.comb += [o_n_validn.eq(~self.o.n_valid),
++                     i_p_valid_o_p_ready.eq(self.i.p_valid & self.o.p_ready),
+         ]
+ 
+         # store result of processing in combinatorial temporary
+-        with m.If(self.i_p_stb): # input is valid: process it
++        with m.If(self.i.p_valid): # input is valid: process it
+             m.d.comb += self.stage.process()
+         # if not in stall condition, update the temporary register
+-        with m.If(o_p_busyn): # not stalled
++        with m.If(self.o.p_ready): # not stalled
+             m.d.sync += self.stage.update_buffer()
+ 
+-        #with m.If(self.i_p_rst): # reset
+-        #    m.d.sync += self.o_n_stb.eq(0)
+-        #    m.d.sync += self.o_p_busy.eq(0)
+-        with m.If(i_n_busyn): # next stage is not busy
+-            with m.If(o_p_busyn): # not stalled
++        #with m.If(self.i.p_rst): # reset
++        #    m.d.sync += self.o.n_valid.eq(0)
++        #    m.d.sync += self.o.p_ready.eq(0)
++        with m.If(self.i.n_ready): # next stage is ready
++            with m.If(self.o.p_ready): # not stalled
+                 # nothing in buffer: send (processed) input direct to output
+-                m.d.sync += [self.o_n_stb.eq(self.i_p_stb),
++                m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
+                              self.stage.update_output(),
+                             ]
+-            with m.Else(): # o_p_busy is true, and something is in our buffer.
++            with m.Else(): # o.p_ready is false, and something is in buffer.
+                 # Flush the [already processed] buffer to the output port.
+-                m.d.sync += [self.o_n_stb.eq(1),
++                m.d.sync += [self.o.n_valid.eq(1),
+                              self.stage.flush_buffer(),
+                              # clear stall condition, declare register empty.
+-                             self.o_p_busy.eq(0),
++                             self.o.p_ready.eq(1),
+                             ]
+-                # ignore input, since o_p_busy is also true.
++                # ignore input, since o.p_ready is also false.
+ 
+-        # (i_n_busy) is true here: next stage is busy
+-        with m.Elif(o_n_stbn): # next stage being told "not busy"
+-            m.d.sync += [self.o_n_stb.eq(self.i_p_stb),
+-                         self.o_p_busy.eq(0), # Keep the buffer empty
++        # (i.n_ready) is false here: next stage is ready
++        with m.Elif(o_n_validn): # next stage being told "ready"
++            m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
++                         self.o.p_ready.eq(1), # Keep the buffer empty
+                          # set the output data (from comb result)
+                          self.stage.update_output(),
+                         ]
+-        # (i_n_busy) and (o_n_stb) both true:
+-        with m.Elif(i_p_stb_o_p_busyn):
+-            # If next stage *is* busy, and not stalled yet, accept input
+-            m.d.sync += self.o_p_busy.eq(self.i_p_stb & self.o_n_stb)
++        # (i.n_ready) false and (o.n_valid) true:
++        with m.Elif(i_p_valid_o_p_ready):
++            # If next stage *is* ready, and not stalled yet, accept input
++            m.d.sync += self.o.p_ready.eq(~(self.i.p_valid & self.o.n_valid))
+ 
+         return m
+ 
+     def ports(self):
+-        return [self.i_p_stb, self.i_n_busy,
+-                self.o_n_stb, self.o_p_busy,
++        return [self.i.p_valid, self.i.n_ready,
++                self.o.n_valid, self.o.p_ready,
+                ]
+ 
+ 
+-class BufPipe(BufferedPipeline):
++class ExampleBufPipe(BufferedPipeline):
+ 
+     def __init__(self):
+         BufferedPipeline.__init__(self)
+diff --git a/src/add/fmul.py b/src/add/fmul.py
+index 130d49e..5b6da94 100644
+--- a/src/add/fmul.py
++++ b/src/add/fmul.py
+@@ -2,7 +2,8 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const
+ from nmigen.cli import main, verilog
+ 
+ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+-from nmigen_add_experiment import FPState
+++from nmigen_add_experiment import FPState, FPGetOp
++
+ 
+ class FPMUL(FPBase):
+ 
+diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
+index ff4c966..e074c5c 100644
+--- a/src/add/nmigen_div_experiment.py
++++ b/src/add/nmigen_div_experiment.py
+@@ -6,6 +6,7 @@ from nmigen import Module, Signal, Const, Cat
+ from nmigen.cli import main, verilog
+ 
+ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
++from nmigen_add_experiment import FPState, FPGetOp
+ 
+ class Div:
+     def __init__(self, width):
+@@ -36,6 +37,12 @@ class FPDIV(FPBase):
+         self.in_b  = FPOp(width)
+         self.out_z = FPOp(width)
+ 
++        self.states = []
++
++    def add_state(self, state):
++        self.states.append(state)
++        return state
++
+     def get_fragment(self, platform=None):
+         """ creates the HDL code-fragment for FPDiv
+         """
+@@ -59,14 +66,26 @@ class FPDIV(FPBase):
+             # ******
+             # gets operand a
+ 
++            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)
++            geta.setup(m, self.in_a)
++
+             with m.State("get_a"):
+-                self.get_op(m, self.in_a, a, "get_b")
++                geta.action(m)
++                with m.If(geta.out_decode):
++                    m.d.sync += a.decode(self.in_a.v)
++                #self.get_op(m, self.in_a, a, "get_b")
+ 
+             # ******
+             # gets operand b
+ 
++            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)
++            getb.setup(m, self.in_b)
++
+             with m.State("get_b"):
+-                self.get_op(m, self.in_b, b, "special_cases")
++                getb.action(m)
++                with m.If(getb.out_decode):
++                    m.d.sync += b.decode(self.in_b.v)
++                #self.get_op(m, self.in_b, b, "special_cases")
+ 
+             # ******
+             # special cases: NaNs, infs, zeros, denormalised
+diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
+index 8590cca..fa23eac 100644
+--- a/src/add/test_buf_pipe.py
++++ b/src/add/test_buf_pipe.py
+@@ -1,86 +1,90 @@
+ from nmigen import Module, Signal
+ from nmigen.compat.sim import run_simulation
+-from example_buf_pipe import BufPipe
++from example_buf_pipe import ExampleBufPipe
+ from random import randint
+ 
+ 
+-def check_o_n_stb(dut, val):
+-    o_n_stb = yield dut.o_n_stb
+-    assert o_n_stb == val
++def check_o_n_valid(dut, val):
++    o_n_valid = yield dut.o.n_valid
++    assert o_n_valid == val
++
++def check_o_n_valid2(dut, val):
++    o_n_valid = yield dut.o_n_valid
++    assert o_n_valid == val
+ 
+ 
+ def testbench(dut):
+     #yield dut.i_p_rst.eq(1)
+-    yield dut.i_n_busy.eq(1)
+-    yield dut.o_p_busy.eq(1)
++    yield dut.i.n_ready.eq(0)
++    yield dut.o.p_ready.eq(0)
+     yield
+     yield
+     #yield dut.i_p_rst.eq(0)
+-    yield dut.i_n_busy.eq(0)
++    yield dut.i.n_ready.eq(1)
+     yield dut.stage.i_data.eq(5)
+-    yield dut.i_p_stb.eq(1)
++    yield dut.i.p_valid.eq(1)
+     yield
+ 
+     yield dut.stage.i_data.eq(7)
+-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed
++    yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
+     yield
+-    yield from check_o_n_stb(dut, 1) # ok *now* i_p_stb effect is felt
++    yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
+ 
+     yield dut.stage.i_data.eq(2)
+     yield
+-    yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
++    yield dut.i.n_ready.eq(0) # begin going into "stall" (next stage says ready)
+     yield dut.stage.i_data.eq(9)
+     yield
+-    yield dut.i_p_stb.eq(0)
++    yield dut.i.p_valid.eq(0)
+     yield dut.stage.i_data.eq(12)
+     yield
+     yield dut.stage.i_data.eq(32)
+-    yield dut.i_n_busy.eq(0)
++    yield dut.i.n_ready.eq(1)
+     yield
+-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
++    yield from check_o_n_valid(dut, 1) # buffer still needs to output
+     yield
+-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
++    yield from check_o_n_valid(dut, 1) # buffer still needs to output
+     yield
+-    yield from check_o_n_stb(dut, 0) # buffer outputted, *now* we're done.
++    yield from check_o_n_valid(dut, 0) # buffer outputted, *now* we're done.
+     yield
+ 
+ 
+ def testbench2(dut):
+-    #yield dut.i_p_rst.eq(1)
+-    yield dut.i_n_busy.eq(1)
+-    #yield dut.o_p_busy.eq(1)
++    #yield dut.i.p_rst.eq(1)
++    yield dut.i_n_ready.eq(0)
++    #yield dut.o.p_ready.eq(0)
+     yield
+     yield
+-    #yield dut.i_p_rst.eq(0)
+-    yield dut.i_n_busy.eq(0)
++    #yield dut.i.p_rst.eq(0)
++    yield dut.i_n_ready.eq(1)
+     yield dut.i_data.eq(5)
+-    yield dut.i_p_stb.eq(1)
++    yield dut.i_p_valid.eq(1)
+     yield
+ 
+     yield dut.i_data.eq(7)
+-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed 2 clocks
++    yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
+     yield
+-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed 2 clocks
++    yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
+ 
+     yield dut.i_data.eq(2)
+     yield
+-    yield from check_o_n_stb(dut, 1) # ok *now* i_p_stb effect is felt
+-    yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
++    yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
++    yield dut.i_n_ready.eq(0) # begin going into "stall" (next stage says ready)
+     yield dut.i_data.eq(9)
+     yield
+-    yield dut.i_p_stb.eq(0)
++    yield dut.i_p_valid.eq(0)
+     yield dut.i_data.eq(12)
+     yield
+     yield dut.i_data.eq(32)
+-    yield dut.i_n_busy.eq(0)
++    yield dut.i_n_ready.eq(1)
+     yield
+-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
++    yield from check_o_n_valid2(dut, 1) # buffer still needs to output
+     yield
+-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
++    yield from check_o_n_valid2(dut, 1) # buffer still needs to output
+     yield
+-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
++    yield from check_o_n_valid2(dut, 1) # buffer still needs to output
+     yield
+-    yield from check_o_n_stb(dut, 0) # buffer outputted, *now* we're done.
++    yield from check_o_n_valid2(dut, 0) # buffer outputted, *now* we're done.
+     yield
+     yield
+     yield
+@@ -104,28 +108,28 @@ class Test3:
+                     send = True
+                 else:
+                     send = randint(0, send_range) != 0
+-                o_p_busy = yield self.dut.o_p_busy
+-                if o_p_busy:
++                o_p_ready = yield self.dut.o.p_ready
++                if not o_p_ready:
+                     yield
+                     continue
+                 if send and self.i != len(self.data):
+-                    yield self.dut.i_p_stb.eq(1)
++                    yield self.dut.i.p_valid.eq(1)
+                     yield self.dut.stage.i_data.eq(self.data[self.i])
+                     self.i += 1
+                 else:
+-                    yield self.dut.i_p_stb.eq(0)
++                    yield self.dut.i.p_valid.eq(0)
+                 yield
+ 
+     def rcv(self):
+         while self.o != len(self.data):
+             stall_range = randint(0, 3)
+             for j in range(randint(1,10)):
+-                stall = randint(0, stall_range) == 0
+-                yield self.dut.i_n_busy.eq(stall)
++                stall = randint(0, stall_range) != 0
++                yield self.dut.i.n_ready.eq(stall)
+                 yield
+-                o_n_stb = yield self.dut.o_n_stb
+-                i_n_busy = yield self.dut.i_n_busy
+-                if not o_n_stb or i_n_busy:
++                o_n_valid = yield self.dut.o.n_valid
++                i_n_ready = yield self.dut.i.n_ready
++                if not o_n_valid or not i_n_ready:
+                     continue
+                 o_data = yield self.dut.stage.o_data
+                 assert o_data == self.data[self.o] + 1, \
+@@ -144,21 +148,21 @@ def testbench4(dut):
+     i = 0
+     o = 0
+     while True:
+-        stall = randint(0, 3) == 0
++        stall = randint(0, 3) != 0
+         send = randint(0, 5) != 0
+-        yield dut.i_n_busy.eq(stall)
+-        o_p_busy = yield dut.o_p_busy
+-        if not o_p_busy:
++        yield dut.i_n_ready.eq(stall)
++        o_p_ready = yield dut.o_p_ready
++        if o_p_ready:
+             if send and i != len(data):
+-                yield dut.i_p_stb.eq(1)
++                yield dut.i_p_valid.eq(1)
+                 yield dut.i_data.eq(data[i])
+                 i += 1
+             else:
+-                yield dut.i_p_stb.eq(0)
++                yield dut.i_p_valid.eq(0)
+         yield
+-        o_n_stb = yield dut.o_n_stb
+-        i_n_busy = yield dut.i_n_busy
+-        if o_n_stb and not i_n_busy:
++        o_n_valid = yield dut.o_n_valid
++        i_n_ready = yield dut.i_n_ready
++        if o_n_valid and i_n_ready:
+             o_data = yield dut.o_data
+             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
+                                         % (i, o, o_data, data[o])
+@@ -167,26 +171,26 @@ def testbench4(dut):
+                 break
+ 
+ 
+-class BufPipe2:
++class ExampleBufPipe2:
+     """
+         connect these:  ------|---------------|
+                               v               v
+-        i_p_stb  >>in  pipe1 o_n_stb  out>> i_p_stb  >>in  pipe2
+-        o_p_busy <<out pipe1 i_n_busy <<in  o_p_busy <<out pipe2
++        i_p_valid  >>in  pipe1 o_n_valid  out>> i_p_valid  >>in  pipe2
++        o_p_ready <<out pipe1 i_n_ready <<in  o_p_ready <<out pipe2
+         stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2
+     """
+     def __init__(self):
+-        self.pipe1 = BufPipe()
+-        self.pipe2 = BufPipe()
++        self.pipe1 = ExampleBufPipe()
++        self.pipe2 = ExampleBufPipe()
+ 
+         # input
+-        self.i_p_stb = Signal()    # >>in - comes in from PREVIOUS stage
+-        self.i_n_busy = Signal()   # in<< - comes in from the NEXT stage
++        self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage
++        self.i_n_ready = Signal()   # in<< - comes in from the NEXT stage
+         self.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage
+ 
+         # output
+-        self.o_n_stb = Signal()    # out>> - goes out to the NEXT stage
+-        self.o_p_busy = Signal()   # <<out - goes out to the PREVIOUS stage
++        self.o_n_valid = Signal()    # out>> - goes out to the NEXT stage
++        self.o_p_ready = Signal()   # <<out - goes out to the PREVIOUS stage
+         self.o_data = Signal(32) # out>> - goes out to the NEXT stage
+ 
+     def elaborate(self, platform):
+@@ -194,37 +198,37 @@ class BufPipe2:
+         m.submodules.pipe1 = self.pipe1
+         m.submodules.pipe2 = self.pipe2
+ 
+-        # connect inter-pipe input/output stb/busy/data
+-        m.d.comb += self.pipe2.i_p_stb.eq(self.pipe1.o_n_stb)
+-        m.d.comb += self.pipe1.i_n_busy.eq(self.pipe2.o_p_busy)
++        # connect inter-pipe input/output valid/ready/data
++        m.d.comb += self.pipe2.i.p_valid.eq(self.pipe1.o.n_valid)
++        m.d.comb += self.pipe1.i.n_ready.eq(self.pipe2.o.p_ready)
+         m.d.comb += self.pipe2.stage.i_data.eq(self.pipe1.stage.o_data)
+ 
+         # inputs/outputs to the module: pipe1 connections here (LHS)
+-        m.d.comb += self.pipe1.i_p_stb.eq(self.i_p_stb)
+-        m.d.comb += self.o_p_busy.eq(self.pipe1.o_p_busy)
++        m.d.comb += self.pipe1.i.p_valid.eq(self.i_p_valid)
++        m.d.comb += self.o_p_ready.eq(self.pipe1.o.p_ready)
+         m.d.comb += self.pipe1.stage.i_data.eq(self.i_data)
+ 
+         # now pipe2 connections (RHS)
+-        m.d.comb += self.o_n_stb.eq(self.pipe2.o_n_stb)
+-        m.d.comb += self.pipe2.i_n_busy.eq(self.i_n_busy)
++        m.d.comb += self.o_n_valid.eq(self.pipe2.o.n_valid)
++        m.d.comb += self.pipe2.i.n_ready.eq(self.i_n_ready)
+         m.d.comb += self.o_data.eq(self.pipe2.stage.o_data)
+ 
+         return m
+ 
+ if __name__ == '__main__':
+     print ("test 1")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
+ 
+     print ("test 2")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
+ 
+     print ("test 3")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     test = Test3(dut)
+     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
+ 
+     print ("test 4")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
+diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
+index ca8523d..bb68861 100644
+--- a/src/add/test_inputgroup.py
++++ b/src/add/test_inputgroup.py
+@@ -99,9 +99,81 @@ def testbench(dut):
+     assert out_mid == 3, "out mid %d" % out_mid
+ 
+ 
++class InputTest:
++    def __init__(self, dut):
++        self.dut = dut
++        self.di = {}
++        self.do = {}
++        self.tlen = 10
++        for mid in range(dut.num_rows):
++            self.di[mid] = {}
++            self.do[mid] = {}
++            for i in range(self.tlen):
++                self.di[mid][i] = randint(0, 100)
++                self.do[mid][i] = self.di[mid][i]
++
++    def send(self, mid):
++        for i in range(self.tlen):
++            op2 = self.di[mid][i]
++            rs = dut.rs[mid]
++            ack = yield rs.ack
++            while not ack:
++                yield
++                ack = yield rs.ack
++            yield rs.in_op[0].eq(i)
++            yield rs.in_op[1].eq(op2)
++            yield rs.stb.eq(0b11) # strobe indicate 1st op ready
++            ack = yield rs.ack
++            while ack:
++                yield
++                ack = yield rs.ack
++            yield rs.stb.eq(0)
++
++            # wait random period of time before queueing another value
++            for i in range(randint(0, 12)):
++                yield
++
++    def recv(self):
++        while True:
++            stb = yield dut.out_op.stb
++            yield dut.out_op.ack.eq(0)
++            while not stb:
++                yield
++                stb = yield dut.out_op.stb
++
++            yield dut.out_op.ack.eq(1)
++            stb = yield dut.out_op.stb
++            while stb:
++                yield
++                stb = yield dut.out_op.stb
++            mid = yield dut.mid
++            out_i = yield dut.out_op.v[0]
++            out_v = yield dut.out_op.v[1]
++
++            # see if this output has occurred already, delete it if it has
++            assert out_i in self.do[mid]
++            assert self.do[mid][out_i] == out_v
++            del self.do[mid][out_i]
++
++            # check if there's any more outputs
++            zerolen = True
++            for (k, v) in self.do.items():
++                if v:
++                    zerolen = False
++            if zerolen:
++                break
++
+ if __name__ == '__main__':
+     dut = InputGroup(width=32)
+     vl = rtlil.convert(dut, ports=dut.ports())
+     with open("test_inputgroup.il", "w") as f:
+         f.write(vl)
+     run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
++
++    dut = InputGroup(width=16)
++    test = InputTest(dut)
++    run_simulation(dut, [test.send(3), test.send(2),
++                         test.send(1), test.send(0),
++                         test.recv()],
++                   vcd_name="test_inputgroup_parallel.vcd")
++
diff --git a/ca218a65 b/ca218a65
new file mode 100644
index 00000000..954bcee9
--- /dev/null
+++ b/ca218a65
@@ -0,0 +1,599 @@
+diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
+index 2604262..00eecc3 100644
+--- a/src/add/example_buf_pipe.py
++++ b/src/add/example_buf_pipe.py
+@@ -203,7 +203,7 @@ class BufferedPipeline:
+                ]
+ 
+ 
+-class BufPipe(BufferedPipeline):
++class ExampleBufPipe(BufferedPipeline):
+ 
+     def __init__(self):
+         BufferedPipeline.__init__(self)
+diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
+index eb0c935..e074c5c 100644
+--- a/src/add/nmigen_div_experiment.py
++++ b/src/add/nmigen_div_experiment.py
+@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Const, Cat
+ from nmigen.cli import main, verilog
+ 
+ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+-from nmigen_add_experiment import FPState
++from nmigen_add_experiment import FPState, FPGetOp
+ 
+ class Div:
+     def __init__(self, width):
+@@ -66,14 +66,26 @@ class FPDIV(FPBase):
+             # ******
+             # gets operand a
+ 
++            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)
++            geta.setup(m, self.in_a)
++
+             with m.State("get_a"):
+-                self.get_op(m, self.in_a, a, "get_b")
++                geta.action(m)
++                with m.If(geta.out_decode):
++                    m.d.sync += a.decode(self.in_a.v)
++                #self.get_op(m, self.in_a, a, "get_b")
+ 
+             # ******
+             # gets operand b
+ 
++            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)
++            getb.setup(m, self.in_b)
++
+             with m.State("get_b"):
+-                self.get_op(m, self.in_b, b, "special_cases")
++                getb.action(m)
++                with m.If(getb.out_decode):
++                    m.d.sync += b.decode(self.in_b.v)
++                #self.get_op(m, self.in_b, b, "special_cases")
+ 
+             # ******
+             # special cases: NaNs, infs, zeros, denormalised
+diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
+index 2a06893..fa23eac 100644
+--- a/src/add/test_buf_pipe.py
++++ b/src/add/test_buf_pipe.py
+@@ -1,6 +1,6 @@
+ from nmigen import Module, Signal
+ from nmigen.compat.sim import run_simulation
+-from example_buf_pipe import BufPipe
++from example_buf_pipe import ExampleBufPipe
+ from random import randint
+ 
+ 
+@@ -171,7 +171,7 @@ def testbench4(dut):
+                 break
+ 
+ 
+-class BufPipe2:
++class ExampleBufPipe2:
+     """
+         connect these:  ------|---------------|
+                               v               v
+@@ -180,8 +180,8 @@ class BufPipe2:
+         stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2
+     """
+     def __init__(self):
+-        self.pipe1 = BufPipe()
+-        self.pipe2 = BufPipe()
++        self.pipe1 = ExampleBufPipe()
++        self.pipe2 = ExampleBufPipe()
+ 
+         # input
+         self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage
+@@ -217,18 +217,18 @@ class BufPipe2:
+ 
+ if __name__ == '__main__':
+     print ("test 1")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
+ 
+     print ("test 2")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
+ 
+     print ("test 3")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     test = Test3(dut)
+     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
+ 
+     print ("test 4")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
+diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
+index ca8523d..bb68861 100644
+--- a/src/add/test_inputgroup.py
++++ b/src/add/test_inputgroup.py
+@@ -99,9 +99,81 @@ def testbench(dut):
+     assert out_mid == 3, "out mid %d" % out_mid
+ 
+ 
++class InputTest:
++    def __init__(self, dut):
++        self.dut = dut
++        self.di = {}
++        self.do = {}
++        self.tlen = 10
++        for mid in range(dut.num_rows):
++            self.di[mid] = {}
++            self.do[mid] = {}
++            for i in range(self.tlen):
++                self.di[mid][i] = randint(0, 100)
++                self.do[mid][i] = self.di[mid][i]
++
++    def send(self, mid):
++        for i in range(self.tlen):
++            op2 = self.di[mid][i]
++            rs = dut.rs[mid]
++            ack = yield rs.ack
++            while not ack:
++                yield
++                ack = yield rs.ack
++            yield rs.in_op[0].eq(i)
++            yield rs.in_op[1].eq(op2)
++            yield rs.stb.eq(0b11) # strobe indicate 1st op ready
++            ack = yield rs.ack
++            while ack:
++                yield
++                ack = yield rs.ack
++            yield rs.stb.eq(0)
++
++            # wait random period of time before queueing another value
++            for i in range(randint(0, 12)):
++                yield
++
++    def recv(self):
++        while True:
++            stb = yield dut.out_op.stb
++            yield dut.out_op.ack.eq(0)
++            while not stb:
++                yield
++                stb = yield dut.out_op.stb
++
++            yield dut.out_op.ack.eq(1)
++            stb = yield dut.out_op.stb
++            while stb:
++                yield
++                stb = yield dut.out_op.stb
++            mid = yield dut.mid
++            out_i = yield dut.out_op.v[0]
++            out_v = yield dut.out_op.v[1]
++
++            # see if this output has occurred already, delete it if it has
++            assert out_i in self.do[mid]
++            assert self.do[mid][out_i] == out_v
++            del self.do[mid][out_i]
++
++            # check if there's any more outputs
++            zerolen = True
++            for (k, v) in self.do.items():
++                if v:
++                    zerolen = False
++            if zerolen:
++                break
++
+ if __name__ == '__main__':
+     dut = InputGroup(width=32)
+     vl = rtlil.convert(dut, ports=dut.ports())
+     with open("test_inputgroup.il", "w") as f:
+         f.write(vl)
+     run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
++
++    dut = InputGroup(width=16)
++    test = InputTest(dut)
++    run_simulation(dut, [test.send(3), test.send(2),
++                         test.send(1), test.send(0),
++                  diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
+index 2604262..00eecc3 100644
+--- a/src/add/example_buf_pipe.py
++++ b/src/add/example_buf_pipe.py
+@@ -203,7 +203,7 @@ class BufferedPipeline:
+                ]
+ 
+ 
+-class BufPipe(BufferedPipeline):
++class ExampleBufPipe(BufferedPipeline):
+ 
+     def __init__(self):
+         BufferedPipeline.__init__(self)
+diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
+index eb0c935..e074c5c 100644
+--- a/src/add/nmigen_div_experiment.py
++++ b/src/add/nmigen_div_experiment.py
+@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Const, Cat
+ from nmigen.cli import main, verilog
+ 
+ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+-from nmigen_add_experiment import FPState
++from nmigen_add_experiment import FPState, FPGetOp
+ 
+ class Div:
+     def __init__(self, width):
+@@ -66,14 +66,26 @@ class FPDIV(FPBase):
+             # ******
+             # gets operand a
+ 
++            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)
++            geta.setup(m, self.in_a)
++
+             with m.State("get_a"):
+-                self.get_op(m, self.in_a, a, "get_b")
++                geta.action(m)
++                with m.If(geta.out_decode):
++                    m.d.sync += a.decode(self.in_a.v)
++                #self.get_op(m, self.in_a, a, "get_b")
+ 
+             # ******
+             # gets operand b
+ 
++            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)
++            getb.setup(m, self.in_b)
++
+             with m.State("get_b"):
+-                self.get_op(m, self.in_b, b, "special_cases")
++                getb.action(m)
++                with m.If(getb.out_decode):
++                    m.d.sync += b.decode(self.in_b.v)
++                #self.get_op(m, self.in_b, b, "special_cases")
+ 
+             # ******
+             # special cases: NaNs, infs, zeros, denormalised
+diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
+index 2a06893..fa23eac 100644
+--- a/src/add/test_buf_pipe.py
++++ b/src/add/test_buf_pipe.py
+@@ -1,6 +1,6 @@
+ from nmigen import Module, Signal
+ from nmigen.compat.sim import run_simulation
+-from example_buf_pipe import BufPipe
++from example_buf_pipe import ExampleBufPipe
+ from random import randint
+ 
+ 
+@@ -171,7 +171,7 @@ def testbench4(dut):
+                 break
+ 
+ 
+-class BufPipe2:
++class ExampleBufPipe2:
+     """
+         connect these:  ------|---------------|
+                               v               v
+@@ -180,8 +180,8 @@ class BufPipe2:
+         stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2
+     """
+     def __init__(self):
+-        self.pipe1 = BufPipe()
+-        self.pipe2 = BufPipe()
++        self.pipe1 = ExampleBufPipe()
++        self.pipe2 = ExampleBufPipe()
+ 
+         # input
+         self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage
+@@ -217,18 +217,18 @@ class BufPipe2:
+ 
+ if __name__ == '__main__':
+     print ("test 1")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
+ 
+     print ("test 2")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
+ 
+     print ("test 3")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     test = Test3(dut)
+     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
+ 
+     print ("test 4")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
+diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
+index ca8523d..bb68861 100644
+--- a/src/add/test_inputgroup.py
++++ b/src/add/test_inputgroup.py
+@@ -99,9 +99,81 @@ def testbench(dut):
+     assert out_mid == 3, "out mid %d" % out_mid
+ 
+ 
++class InputTest:
++    def __init__(self, dut):
++        self.dut = dut
++        self.di = {}
++        self.do = {}
++        self.tlen = 10
++        for mid in range(dut.num_rows):
++            self.di[mid] = {}
++            self.do[mid] = {}
++            for i in range(self.tlen):
++                self.di[mid][i] = randint(0, 100)
++                self.do[mid][i] = self.di[mid][i]
++
++    def send(self, mid):
++        for i in range(self.tlen):
++            op2 = self.di[mid][i]
++            rs = dut.rs[mid]
++            ack = yield rs.ack
++            while not ack:
++                yield
++                ack = yield rs.ack
++            yield rs.in_op[0].eq(i)
++            yield rs.in_op[1].eq(op2)
++            yield rs.stb.eq(0b11) # strobe indicate 1st op ready
++            ack = yield rs.ack
++            while ack:
++                yield
++                ack = yield rs.ack
++            yield rs.stb.eq(0)
++
++            # wait random period of time before queueing another value
++            for i in range(randint(0, 12)):
++                yield
++
++    def recv(self):
++        while True:
++            stb = yield dut.out_op.stb
++            yield dut.out_op.ack.eq(0)
++            while not stb:
++                yield
++                stb = yield dut.out_op.stb
++
++            yield dut.out_op.ack.eq(1)
++            stb = yield dut.out_op.stb
++            while stb:
++                yield
++                stb = yield dut.out_op.stb
++            mid = yield dut.mid
++            out_i = yield dut.out_op.v[0]
++            out_v = yield dut.out_op.v[1]
++
++            # see if this output has occurred already, delete it if it has
++            assert out_i in self.do[mid]
++            assert self.do[mid][out_i] == out_v
++            del self.do[mid][out_i]
++
++            # check if there's any more outputs
++            zerolen = True
++            for (k, v) in self.do.items():
++                if v:
++                    zerolen = False
++            if zerolen:
++                break
++
+ if __name__ == '__main__':
+     dut = InputGroup(width=32)
+     vl = rtlil.convert(dut, ports=dut.ports())
+     with open("test_inputgroup.il", "w") as f:
+         f.write(vl)
+     run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
++
++    dut = InputGroup(width=16)
++    test = InputTest(dut)
++    run_simulation(dut, [test.send(3), test.send(2),
++                         test.send(1), test.send(0),
++                         test.recv()],
++                   vcd_name="test_inputgroup_parallel.vcd")
++
+diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
+index 2604262..00eecc3 100644
+--- a/src/add/example_buf_pipe.py
++++ b/src/add/example_buf_pipe.py
+@@ -203,7 +203,7 @@ class BufferedPipeline:
+                ]
+ 
+ 
+-class BufPipe(BufferedPipeline):
++class ExampleBufPipe(BufferedPipeline):
+ 
+     def __init__(self):
+         BufferedPipeline.__init__(self)
+diff --git a/src/add/fmul.py b/src/add/fmul.py
+index 130d49e..5b6da94 100644
+--- a/src/add/fmul.py
++++ b/src/add/fmul.py
+@@ -2,7 +2,8 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const
+ from nmigen.cli import main, verilog
+ 
+ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+-from nmigen_add_experiment import FPState
+++from nmigen_add_experiment import FPState, FPGetOp
++
+ 
+ class FPMUL(FPBase):
+ 
+diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
+index eb0c935..e074c5c 100644
+--- a/src/add/nmigen_div_experiment.py
++++ b/src/add/nmigen_div_experiment.py
+@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Const, Cat
+ from nmigen.cli import main, verilog
+ 
+ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+-from nmigen_add_experiment import FPState
++from nmigen_add_experiment import FPState, FPGetOp
+ 
+ class Div:
+     def __init__(self, width):
+@@ -66,14 +66,26 @@ class FPDIV(FPBase):
+             # ******
+             # gets operand a
+ 
++            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)
++            geta.setup(m, self.in_a)
++
+             with m.State("get_a"):
+-                self.get_op(m, self.in_a, a, "get_b")
++                geta.action(m)
++                with m.If(geta.out_decode):
++                    m.d.sync += a.decode(self.in_a.v)
++                #self.get_op(m, self.in_a, a, "get_b")
+ 
+             # ******
+             # gets operand b
+ 
++            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)
++            getb.setup(m, self.in_b)
++
+             with m.State("get_b"):
+-                self.get_op(m, self.in_b, b, "special_cases")
++                getb.action(m)
++                with m.If(getb.out_decode):
++                    m.d.sync += b.decode(self.in_b.v)
++                #self.get_op(m, self.in_b, b, "special_cases")
+ 
+             # ******
+             # special cases: NaNs, infs, zeros, denormalised
+diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
+index 2a06893..fa23eac 100644
+--- a/src/add/test_buf_pipe.py
++++ b/src/add/test_buf_pipe.py
+@@ -1,6 +1,6 @@
+ from nmigen import Module, Signal
+ from nmigen.compat.sim import run_simulation
+-from example_buf_pipe import BufPipe
++from example_buf_pipe import ExampleBufPipe
+ from random import randint
+ 
+ 
+@@ -171,7 +171,7 @@ def testbench4(dut):
+                 break
+ 
+ 
+-class BufPipe2:
++class ExampleBufPipe2:
+     """
+         connect these:  ------|---------------|
+                               v               v
+@@ -180,8 +180,8 @@ class BufPipe2:
+         stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2
+     """
+     def __init__(self):
+-        self.pipe1 = BufPipe()
+-        self.pipe2 = BufPipe()
++        self.pipe1 = ExampleBufPipe()
++        self.pipe2 = ExampleBufPipe()
+ 
+         # input
+         self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage
+@@ -217,18 +217,18 @@ class BufPipe2:
+ 
+ if __name__ == '__main__':
+     print ("test 1")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
+ 
+     print ("test 2")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
+ 
+     print ("test 3")
+-    dut = BufPipe()
++    dut = ExampleBufPipe()
+     test = Test3(dut)
+     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
+ 
+     print ("test 4")
+-    dut = BufPipe2()
++    dut = ExampleBufPipe2()
+     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")
+diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
+index ca8523d..bb68861 100644
+--- a/src/add/test_inputgroup.py
++++ b/src/add/test_inputgroup.py
+@@ -99,9 +99,81 @@ def testbench(dut):
+     assert out_mid == 3, "out mid %d" % out_mid
+ 
+ 
++class InputTest:
++    def __init__(self, dut):
++        self.dut = dut
++        self.di = {}
++        self.do = {}
++        self.tlen = 10
++        for mid in range(dut.num_rows):
++            self.di[mid] = {}
++            self.do[mid] = {}
++            for i in range(self.tlen):
++                self.di[mid][i] = randint(0, 100)
++                self.do[mid][i] = self.di[mid][i]
++
++    def send(self, mid):
++        for i in range(self.tlen):
++            op2 = self.di[mid][i]
++            rs = dut.rs[mid]
++            ack = yield rs.ack
++            while not ack:
++                yield
++                ack = yield rs.ack
++            yield rs.in_op[0].eq(i)
++            yield rs.in_op[1].eq(op2)
++            yield rs.stb.eq(0b11) # strobe indicate 1st op ready
++            ack = yield rs.ack
++            while ack:
++                yield
++                ack = yield rs.ack
++            yield rs.stb.eq(0)
++
++            # wait random period of time before queueing another value
++            for i in range(randint(0, 12)):
++                yield
++
++    def recv(self):
++        while True:
++            stb = yield dut.out_op.stb
++            yield dut.out_op.ack.eq(0)
++            while not stb:
++                yield
++                stb = yield dut.out_op.stb
++
++            yield dut.out_op.ack.eq(1)
++            stb = yield dut.out_op.stb
++            while stb:
++                yield
++                stb = yield dut.out_op.stb
++            mid = yield dut.mid
++            out_i = yield dut.out_op.v[0]
++            out_v = yield dut.out_op.v[1]
++
++            # see if this output has occurred already, delete it if it has
++            assert out_i in self.do[mid]
++            assert self.do[mid][out_i] == out_v
++            del self.do[mid][out_i]
++
++            # check if there's any more outputs
++            zerolen = True
++            for (k, v) in self.do.items():
++                if v:
++                    zerolen = False
++            if zerolen:
++                break
++
+ if __name__ == '__main__':
+     dut = InputGroup(width=32)
+     vl = rtlil.convert(dut, ports=dut.ports())
+     with open("test_inputgroup.il", "w") as f:
+         f.write(vl)
+     run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
++
++    dut = InputGroup(width=16)
++    test = InputTest(dut)
++    run_simulation(dut, [test.send(3), test.send(2),
++                         test.send(1), test.send(0),
++                         test.recv()],
++                   vcd_name="test_inputgroup_parallel.vcd")
++
diff --git a/git diff a36447fc^ b/git diff a36447fc^
new file mode 100644
index 00000000..d911455c
--- /dev/null
+++ b/git diff a36447fc^	
@@ -0,0 +1,505 @@
+commit f02c6f4bbf463472d3d68e52bd5ededd3c937f58 (HEAD -> master, origin/master, origin/HEAD)
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 12:37:14 2019 +0000
+
+    add parallel InputGroup unit test
+
+commit b13c8a7a5368a53bedc71e5b8969c721103144c4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 10:59:44 2019 +0000
+
+    rename BufPipe example to ExampleBufPipe
+
+commit a36447fcd4d4f049b7127e1fc02dc1390d05fa75
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:59:07 2019 +0000
+
+    instantiate 2 FPGetOp instances and use them.  a little awkwardly.
+
+commit 092d2d78fa19a5c73863cb89c5d680cbd2afe027
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:33:44 2019 +0000
+
+    update comments
+
+commit 8989cd3452869d43a8a3655acffd3eb3288f5d9a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:22:58 2019 +0000
+
+    remove unnecessary code
+
+commit b90c533476affe63a34292bfe54dde62a105bed8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:47:21 2019 +0000
+
+    add extra comment block explaining pipe stage example
+
+commit 28a8ede4a797a76e83410fb42a9aaa02b44fb2ef
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:37:18 2019 +0000
+
+    inverted busy signal and named it "ready"
+
+commit 0ebc09c0a7b74e4807ccdb60ca0a10cbb605666a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:29:56 2019 +0000
+
+    rename stb to "valid"
+
+commit 0bfbc8ff919f0cd9c7f01b4c711b1b91a53ad480
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:28:18 2019 +0000
+
+    create classes for STB/BUSY, split in from out
+
+commit ca218a65dc9af73965a5c4f105a780ed04b588e0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 00:31:30 2019 +0000
+
+    add use of FPState, not being used yet
+
+commit ce7a1d5c48e987cbfb40236f13b17ffcea55b585
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 13:32:06 2019 +0000
+
+    split pipeline test into 2 functions, one send, one receive
+
+commit 481d00c37b31e7908e624235e6e9c93b12baeebb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 06:33:10 2019 +0000
+
+    got fpdiv up and running again
+
+commit 286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 05:41:02 2019 +0000
+
+    forgot to add submodules
+
+commit 43c53078d577aa33d28ba0eb2af782b7d348a517
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 05:09:36 2019 +0000
+
+    got rounding working again for fmul
+
+commit 892d640f8224e6a52907c6899ab6ab671f5f53af
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:42:53 2019 +0000
+
+    remove extra arg from old roundz function
+
+commit ccd4d65a7bd2985edb5547daf7df623cda5ab9da
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:33:01 2019 +0000
+
+    make a bit of a mess of the unit tests, getting mul up and running again
+    taking a copy (sigh) of the old version of check_case and get_case
+
+commit 9b9732e1c96d085bc9c7b696e7c86dd0c4a4ae49
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:17:28 2019 +0000
+
+    get roundz working again, needed for mul stage
+
+commit 38452d7fb64752a897b26e1da96a27d3a5979a76
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:16:28 2019 +0000
+
+    add new FPNormaliseSingleMod, not tested
+
+commit 3e994c6039c3cce1dbecc6dddd1b6be23af390fb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 03:18:06 2019 +0000
+
+    start to get fpmul back up and running
+
+commit 5ca9e3ee685a261fbff9998ab37940aa3255b9fa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 03:04:33 2019 +0000
+
+    replace copy of FPState with import of FPState
+
+commit af3ae7902ba4e5a26556eb4442c8351c95b267a4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 02:54:57 2019 +0000
+
+    update comments
+
+commit 95cd53141ace92120fccb83a96af96323dea9c0d
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Wed Mar 13 18:39:14 2019 +0100
+
+    Started to update fmul.py to new conventions
+
+commit edf77dc7ee9fa94e1ec07e1ae4616e87c9f7298c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 12:39:09 2019 +0000
+
+    increase data set to throw at pipeline in tests
+
+commit 2ec9fee974fe500ff4e3375d35f6148ef3560e36
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 11:48:10 2019 +0000
+
+    add random-busy, random-send single and dual buffered pipeline tests
+
+commit 1abb4da885f1e66f800c310766924918a3b1474c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 11:01:22 2019 +0000
+
+    split out actual pipeline stage into separate class
+
+commit 9de2c40d3c1051650dd6f29b2ea5a0bd4e67b366
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 07:26:23 2019 +0000
+
+    add 2 stage buffered pipeline unit test, reduce to 16-bit to make vcd clearer
+
+commit b58c1a8f96dfaa63e89c7f3d7fd65f0fec9c1932
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 04:26:24 2019 +0000
+
+    only process data if the input strobe is valid
+
+commit b32f06d6ed5f6639b929d21453c09dee1296db96
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 04:24:50 2019 +0000
+
+    add in some assertions to check pipe output
+
+commit 14559d0d0edaee06af261a04ed0a33a5bd1e0479
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:49:48 2019 +0000
+
+    split out unit test in buf pipe example
+
+commit c10d9619880099356e760c4ae45c8a0b18d1aeac
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:47:49 2019 +0000
+
+    combine blocks to add list of statements, add comments
+
+commit c60a4997aa35ebc32e121d401af06d3bfee9c5c3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:35:41 2019 +0000
+
+    update comments
+
+commit e605dd06dae1fb584a25a526125179da8a6eac2e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:11:05 2019 +0000
+
+    store inv-strobe in temp signal
+
+commit 9432c1a8a962879685df5b4810ccf97db439c1a9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:10:44 2019 +0000
+
+    clean up code
+
+commit 5ecfe07d6d3fde658df517ab48bb515dfae32f26
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 15:14:13 2019 +0000
+
+    store processed input in intermediary
+
+commit 0e70fec7c3df1ee97020aa5be6f358c85898a5fb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 13:22:20 2019 +0000
+
+    add (but comment out) reset signal
+
+commit cfc989aa8b0d4c19a15c6e0d7210dde46bb480e8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 13:14:17 2019 +0000
+
+    add example buffered pipe
+
+commit e1336d2ad072dc6661c9af1b0460a69ff1bf588f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 13:13:33 2019 +0000
+
+    add example buffered pipe
+
+commit 289c5cf9f7510a9e9bc3239155db27bdbd982e70
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 19:09:39 2019 +0000
+
+    get InputGroup running
+
+commit 33b30ebf9210e7a3c03d3babc73ad4ed12b8685e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:54:57 2019 +0000
+
+    add inputgroup test
+
+commit bc8abd924298a632e586b34d072c5437844e8aea
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:54:32 2019 +0000
+
+    Trigger needs to be combinatorial (saves clock cycles)
+
+commit d0c5c2d71fb122797f6a02a6da30c404c0ff90b9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:32:48 2019 +0000
+
+    return mid as part of ports
+
+commit 9245c808cb817d0054b6c9fd9d510a4a722db308
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:32:09 2019 +0000
+
+    whoops, forgot to make input an Array, can use array indexing now
+
+commit 79192af4fd00e42156463bf2a32744a3f4f458ee
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 11:26:45 2019 +0000
+
+    create an FPOps output class to clean up the InputGroup
+
+commit 1fda7bf6bad5c48a295726a9a9cd0df0fc598114
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 11:15:29 2019 +0000
+
+    add capability to pass through operands and muxid to output
+
+commit 3eeb871f5920bdbb365f513440ee3bf57a491e08
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 09:37:19 2019 +0000
+
+    make a start on an InputGroup module
+
+commit dced2d8e93d5653a723fe77eec4f2cf87f004098
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 08:42:21 2019 +0000
+
+    add a multi-input stb/ack module
+    
+    to be used for acknowledging and passing on multiple inputs once all ready
+
+commit a6e7f74fa24d010999e6963ee33d3e078f83cfd2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 07:06:51 2019 +0000
+
+    add result array module
+
+commit bc8d3b3d11ae8e748e12bbb0b985d9ba54f11419
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 08:42:43 2019 +0000
+
+    create array of in/outs however set muxid to zero temporarily
+
+commit 93da24dcd72c6a7a39146c4dba6b5a882e7ef6ca
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 07:05:55 2019 +0000
+
+    store fpadd result in putz, next phase: direct to array of output results
+
+commit 9678f15f0c77d58649d1064e5d7268905da16937
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 03:37:36 2019 +0000
+
+    allow code-creation
+
+commit 9926a532bb3fdd1a7715f5ee3b68847e566e4f0b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 03:34:38 2019 +0000
+
+    create array of in_a, in_b and out_z
+
+commit 52a3d3916b905d3e9e7e7e606c77aa9ab58a4f3d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 03:22:31 2019 +0000
+
+    move ids to member variable
+
+commit 7522c2b5594486cba0e07df28bb74d0733d0ed1b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 11:23:05 2019 +0000
+
+    chain add stage 0 and 1 together with align in combinatorial block
+
+commit 5d1234824040d0903048476297a9be850ee08c54
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 11:11:27 2019 +0000
+
+    create combined combinatorial align and add0
+
+commit 677577b32e8323b0265aa16610f278e019692b97
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 11:01:29 2019 +0000
+
+    merge specialcases and denorm into single combinatorial chain
+
+commit ad26042b4e313d8f1273ff8bac9bac317440bffc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:46:54 2019 +0000
+
+    create specialcasesmod setup fn
+
+commit 5efb9e47fa9eb0529c142b175e0937b64de68d91
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:03:49 2019 +0000
+
+    whoops forgot self.width
+
+commit 698601cec4a9d46dbc4f0a92b66ad5d50a66bc26
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:03:28 2019 +0000
+
+    add comments
+
+commit 2c05d1d4507e0e50e36a02e08a0458b315be0ab3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:00:37 2019 +0000
+
+    move localiseable variables to local function
+
+commit f067330d9c1686e114a93480c3ffb781aac6d6a6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:54:03 2019 +0000
+
+    connect corrections to pack with combinatorial logic
+
+commit f14133ebce3e79e67ff35ff0720b51a3fb6a335c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:34:04 2019 +0000
+
+    connect round directly to corrections with combinatorial logic
+
+commit a641d2526a2d1e2fc7d04b40d41d10e114f0e7f9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:24:50 2019 +0000
+
+    connect normalisation directly to round with combinatorial logic
+
+commit ef144a6f35cf7d9bfc0268d50f1572be1ddf2e13
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:13:47 2019 +0000
+
+    big reorganisation
+    
+    splitting out Normalisation Single/Multi
+    adding beginnings of combinatorial-chained normalisation thru pack
+
+commit 71d97d936d73e8a47cdcc12d1e0888293c90c41e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 07:25:28 2019 +0000
+
+    split out into 2 functions, longer and compact fragment
+
+commit 56bd686dd363a532a9b4843c5c8ff710c24a24bc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 07:18:47 2019 +0000
+
+    move in_t_ack into FPGet2Op setup
+
+commit 0f141d1586b5865638db9626da05c1448578d9aa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 07:18:01 2019 +0000
+
+    add "compact" option
+
+commit 5e20d7a6fb0f8b623634951b64a932e5f2e97a0f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 8 12:59:11 2019 +0000
+
+    main on FPADD not on FPADDBase
+
+commit 4527b5644ba6e6c8d7ee8d1990775ff266011433
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 8 12:53:15 2019 +0000
+
+    big reorg, got FPADD to work using new FPADDBase
+
+commit 25a892466594952291f03b50c5daf29a1335c11f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 21:46:01 2019 +0000
+
+    add some comments to FPAddBase
+
+commit f39188c47f81343121785bad1366a831d115a924
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 12:14:47 2019 +0000
+
+    in the middle of rewiring FPADD to use FPADDBase
+
+commit e768533532bb2035e9cbc78e2db86affc694e290
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 06:09:15 2019 +0000
+
+    split out main stages of add to separate class, FPADDBase
+
+commit 63cd263891fb851e2585add543f9138f7d12710d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 06:08:20 2019 +0000
+
+    add function unit module
+
+commit 3e5ecb581d6b93019e088878231a9d871a2d686b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 06:08:09 2019 +0000
+
+    correct syntax error
+
+commit cbfd9aa5a65e7c0270e0d9fe1fc1667779a4742b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 03:06:04 2019 +0000
+
+    add reservation station row module
+
+commit b8d39c3d5295e7fdeb0e769c2bd84fe929457ef0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:50:36 2019 +0000
+
+    add MID testing
+
+commit cd5a425849b29b810b6ff16216296e286f1dcd27
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:36:50 2019 +0000
+
+    add id to pack and putz
+
+commit 4a10d39f2cb4eda127034a8f021eee6ccdf6de74
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:33:16 2019 +0000
+
+    add id to FPPack
+
+commit 52eb96de2fddee430954899471d10c012b5fd1d2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:30:20 2019 +0000
+
+    add id to FPCorrections
+
+commit 80faa8e2714b5417b40db99294bec8710bb8ec17
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:28:48 2019 +0000
+
+    add id to FPRound
+
+commit 8f9071b7d0a205b6dda40da28c358f1e26e007a0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:26:13 2019 +0000
+
+    add id to norm1
+
+commit e3197c61ce5de2cab4b36fe07b913c526844d328
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:24:54 2019 +0000
+
+    add id to stage1
+
+commit 3956a968ae847f27b3e46ff805dc75c259e1c544
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:22:19 2019 +0000
+
+    add id to stage0
+
+commit 074236f303578939f925f3668c88b7e6cd929c75
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:18:39 2019 +0000
+
+    add id to align
+
+commit 3597dda29683c1b06bd70edc88
\ No newline at end of file
diff --git a/search for a36447fc b/search for a36447fc
new file mode 100644
index 00000000..3b160c8d
--- /dev/null
+++ b/search for a36447fc	
@@ -0,0 +1,2363 @@
+commit f02c6f4bbf463472d3d68e52bd5ededd3c937f58 (HEAD -> master, origin/master, origin/HEAD)
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 12:37:14 2019 +0000
+
+    add parallel InputGroup unit test
+
+commit b13c8a7a5368a53bedc71e5b8969c721103144c4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 10:59:44 2019 +0000
+
+    rename BufPipe example to ExampleBufPipe
+
+commit a36447fcd4d4f049b7127e1fc02dc1390d05fa75
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:59:07 2019 +0000
+
+    instantiate 2 FPGetOp instances and use them.  a little awkwardly.
+
+commit 092d2d78fa19a5c73863cb89c5d680cbd2afe027
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:33:44 2019 +0000
+
+    update comments
+
+commit 8989cd3452869d43a8a3655acffd3eb3288f5d9a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 09:22:58 2019 +0000
+
+    remove unnecessary code
+
+commit b90c533476affe63a34292bfe54dde62a105bed8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:47:21 2019 +0000
+
+    add extra comment block explaining pipe stage example
+
+commit 28a8ede4a797a76e83410fb42a9aaa02b44fb2ef
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:37:18 2019 +0000
+
+    inverted busy signal and named it "ready"
+
+commit 0ebc09c0a7b74e4807ccdb60ca0a10cbb605666a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:29:56 2019 +0000
+
+    rename stb to "valid"
+
+commit 0bfbc8ff919f0cd9c7f01b4c711b1b91a53ad480
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 08:28:18 2019 +0000
+
+    create classes for STB/BUSY, split in from out
+
+commit ca218a65dc9af73965a5c4f105a780ed04b588e0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 15 00:31:30 2019 +0000
+
+    add use of FPState, not being used yet
+
+commit ce7a1d5c48e987cbfb40236f13b17ffcea55b585
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 13:32:06 2019 +0000
+
+    split pipeline test into 2 functions, one send, one receive
+
+commit 481d00c37b31e7908e624235e6e9c93b12baeebb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 06:33:10 2019 +0000
+
+    got fpdiv up and running again
+
+commit 286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 05:41:02 2019 +0000
+
+    forgot to add submodules
+
+commit 43c53078d577aa33d28ba0eb2af782b7d348a517
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 05:09:36 2019 +0000
+
+    got rounding working again for fmul
+
+commit 892d640f8224e6a52907c6899ab6ab671f5f53af
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:42:53 2019 +0000
+
+    remove extra arg from old roundz function
+
+commit ccd4d65a7bd2985edb5547daf7df623cda5ab9da
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:33:01 2019 +0000
+
+    make a bit of a mess of the unit tests, getting mul up and running again
+    taking a copy (sigh) of the old version of check_case and get_case
+
+commit 9b9732e1c96d085bc9c7b696e7c86dd0c4a4ae49
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:17:28 2019 +0000
+
+    get roundz working again, needed for mul stage
+
+commit 38452d7fb64752a897b26e1da96a27d3a5979a76
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 04:16:28 2019 +0000
+
+    add new FPNormaliseSingleMod, not tested
+
+commit 3e994c6039c3cce1dbecc6dddd1b6be23af390fb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 03:18:06 2019 +0000
+
+    start to get fpmul back up and running
+
+commit 5ca9e3ee685a261fbff9998ab37940aa3255b9fa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 03:04:33 2019 +0000
+
+    replace copy of FPState with import of FPState
+
+commit af3ae7902ba4e5a26556eb4442c8351c95b267a4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Mar 14 02:54:57 2019 +0000
+
+    update comments
+
+commit 95cd53141ace92120fccb83a96af96323dea9c0d
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Wed Mar 13 18:39:14 2019 +0100
+
+    Started to update fmul.py to new conventions
+
+commit edf77dc7ee9fa94e1ec07e1ae4616e87c9f7298c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 12:39:09 2019 +0000
+
+    increase data set to throw at pipeline in tests
+
+commit 2ec9fee974fe500ff4e3375d35f6148ef3560e36
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 11:48:10 2019 +0000
+
+    add random-busy, random-send single and dual buffered pipeline tests
+
+commit 1abb4da885f1e66f800c310766924918a3b1474c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 11:01:22 2019 +0000
+
+    split out actual pipeline stage into separate class
+
+commit 9de2c40d3c1051650dd6f29b2ea5a0bd4e67b366
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 07:26:23 2019 +0000
+
+    add 2 stage buffered pipeline unit test, reduce to 16-bit to make vcd clearer
+
+commit b58c1a8f96dfaa63e89c7f3d7fd65f0fec9c1932
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 04:26:24 2019 +0000
+
+    only process data if the input strobe is valid
+
+commit b32f06d6ed5f6639b929d21453c09dee1296db96
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 04:24:50 2019 +0000
+
+    add in some assertions to check pipe output
+
+commit 14559d0d0edaee06af261a04ed0a33a5bd1e0479
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:49:48 2019 +0000
+
+    split out unit test in buf pipe example
+
+commit c10d9619880099356e760c4ae45c8a0b18d1aeac
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:47:49 2019 +0000
+
+    combine blocks to add list of statements, add comments
+
+commit c60a4997aa35ebc32e121d401af06d3bfee9c5c3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:35:41 2019 +0000
+
+    update comments
+
+commit e605dd06dae1fb584a25a526125179da8a6eac2e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:11:05 2019 +0000
+
+    store inv-strobe in temp signal
+
+commit 9432c1a8a962879685df5b4810ccf97db439c1a9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 13 03:10:44 2019 +0000
+
+    clean up code
+
+commit 5ecfe07d6d3fde658df517ab48bb515dfae32f26
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 15:14:13 2019 +0000
+
+    store processed input in intermediary
+
+commit 0e70fec7c3df1ee97020aa5be6f358c85898a5fb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 13:22:20 2019 +0000
+
+    add (but comment out) reset signal
+
+commit cfc989aa8b0d4c19a15c6e0d7210dde46bb480e8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 13:14:17 2019 +0000
+
+    add example buffered pipe
+
+commit e1336d2ad072dc6661c9af1b0460a69ff1bf588f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 12 13:13:33 2019 +0000
+
+    add example buffered pipe
+
+commit 289c5cf9f7510a9e9bc3239155db27bdbd982e70
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 19:09:39 2019 +0000
+
+    get InputGroup running
+
+commit 33b30ebf9210e7a3c03d3babc73ad4ed12b8685e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:54:57 2019 +0000
+
+    add inputgroup test
+
+commit bc8abd924298a632e586b34d072c5437844e8aea
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:54:32 2019 +0000
+
+    Trigger needs to be combinatorial (saves clock cycles)
+
+commit d0c5c2d71fb122797f6a02a6da30c404c0ff90b9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:32:48 2019 +0000
+
+    return mid as part of ports
+
+commit 9245c808cb817d0054b6c9fd9d510a4a722db308
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 12:32:09 2019 +0000
+
+    whoops, forgot to make input an Array, can use array indexing now
+
+commit 79192af4fd00e42156463bf2a32744a3f4f458ee
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 11:26:45 2019 +0000
+
+    create an FPOps output class to clean up the InputGroup
+
+commit 1fda7bf6bad5c48a295726a9a9cd0df0fc598114
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 11:15:29 2019 +0000
+
+    add capability to pass through operands and muxid to output
+
+commit 3eeb871f5920bdbb365f513440ee3bf57a491e08
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 09:37:19 2019 +0000
+
+    make a start on an InputGroup module
+
+commit dced2d8e93d5653a723fe77eec4f2cf87f004098
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 08:42:21 2019 +0000
+
+    add a multi-input stb/ack module
+    
+    to be used for acknowledging and passing on multiple inputs once all ready
+
+commit a6e7f74fa24d010999e6963ee33d3e078f83cfd2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 11 07:06:51 2019 +0000
+
+    add result array module
+
+commit bc8d3b3d11ae8e748e12bbb0b985d9ba54f11419
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 08:42:43 2019 +0000
+
+    create array of in/outs however set muxid to zero temporarily
+
+commit 93da24dcd72c6a7a39146c4dba6b5a882e7ef6ca
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 07:05:55 2019 +0000
+
+    store fpadd result in putz, next phase: direct to array of output results
+
+commit 9678f15f0c77d58649d1064e5d7268905da16937
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 03:37:36 2019 +0000
+
+    allow code-creation
+
+commit 9926a532bb3fdd1a7715f5ee3b68847e566e4f0b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 03:34:38 2019 +0000
+
+    create array of in_a, in_b and out_z
+
+commit 52a3d3916b905d3e9e7e7e606c77aa9ab58a4f3d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 10 03:22:31 2019 +0000
+
+    move ids to member variable
+
+commit 7522c2b5594486cba0e07df28bb74d0733d0ed1b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 11:23:05 2019 +0000
+
+    chain add stage 0 and 1 together with align in combinatorial block
+
+commit 5d1234824040d0903048476297a9be850ee08c54
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 11:11:27 2019 +0000
+
+    create combined combinatorial align and add0
+
+commit 677577b32e8323b0265aa16610f278e019692b97
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 11:01:29 2019 +0000
+
+    merge specialcases and denorm into single combinatorial chain
+
+commit ad26042b4e313d8f1273ff8bac9bac317440bffc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:46:54 2019 +0000
+
+    create specialcasesmod setup fn
+
+commit 5efb9e47fa9eb0529c142b175e0937b64de68d91
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:03:49 2019 +0000
+
+    whoops forgot self.width
+
+commit 698601cec4a9d46dbc4f0a92b66ad5d50a66bc26
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:03:28 2019 +0000
+
+    add comments
+
+commit 2c05d1d4507e0e50e36a02e08a0458b315be0ab3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 10:00:37 2019 +0000
+
+    move localiseable variables to local function
+
+commit f067330d9c1686e114a93480c3ffb781aac6d6a6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:54:03 2019 +0000
+
+    connect corrections to pack with combinatorial logic
+
+commit f14133ebce3e79e67ff35ff0720b51a3fb6a335c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:34:04 2019 +0000
+
+    connect round directly to corrections with combinatorial logic
+
+commit a641d2526a2d1e2fc7d04b40d41d10e114f0e7f9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:24:50 2019 +0000
+
+    connect normalisation directly to round with combinatorial logic
+
+commit ef144a6f35cf7d9bfc0268d50f1572be1ddf2e13
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 09:13:47 2019 +0000
+
+    big reorganisation
+    
+    splitting out Normalisation Single/Multi
+    adding beginnings of combinatorial-chained normalisation thru pack
+
+commit 71d97d936d73e8a47cdcc12d1e0888293c90c41e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 07:25:28 2019 +0000
+
+    split out into 2 functions, longer and compact fragment
+
+commit 56bd686dd363a532a9b4843c5c8ff710c24a24bc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 07:18:47 2019 +0000
+
+    move in_t_ack into FPGet2Op setup
+
+commit 0f141d1586b5865638db9626da05c1448578d9aa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 9 07:18:01 2019 +0000
+
+    add "compact" option
+
+commit 5e20d7a6fb0f8b623634951b64a932e5f2e97a0f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 8 12:59:11 2019 +0000
+
+    main on FPADD not on FPADDBase
+
+commit 4527b5644ba6e6c8d7ee8d1990775ff266011433
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 8 12:53:15 2019 +0000
+
+    big reorg, got FPADD to work using new FPADDBase
+
+commit 25a892466594952291f03b50c5daf29a1335c11f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 21:46:01 2019 +0000
+
+    add some comments to FPAddBase
+
+commit f39188c47f81343121785bad1366a831d115a924
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 12:14:47 2019 +0000
+
+    in the middle of rewiring FPADD to use FPADDBase
+
+commit e768533532bb2035e9cbc78e2db86affc694e290
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 06:09:15 2019 +0000
+
+    split out main stages of add to separate class, FPADDBase
+
+commit 63cd263891fb851e2585add543f9138f7d12710d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 06:08:20 2019 +0000
+
+    add function unit module
+
+commit 3e5ecb581d6b93019e088878231a9d871a2d686b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Mar 6 06:08:09 2019 +0000
+
+    correct syntax error
+
+commit cbfd9aa5a65e7c0270e0d9fe1fc1667779a4742b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 03:06:04 2019 +0000
+
+    add reservation station row module
+
+commit b8d39c3d5295e7fdeb0e769c2bd84fe929457ef0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:50:36 2019 +0000
+
+    add MID testing
+
+commit cd5a425849b29b810b6ff16216296e286f1dcd27
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:36:50 2019 +0000
+
+    add id to pack and putz
+
+commit 4a10d39f2cb4eda127034a8f021eee6ccdf6de74
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:33:16 2019 +0000
+
+    add id to FPPack
+
+commit 52eb96de2fddee430954899471d10c012b5fd1d2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:30:20 2019 +0000
+
+    add id to FPCorrections
+
+commit 80faa8e2714b5417b40db99294bec8710bb8ec17
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:28:48 2019 +0000
+
+    add id to FPRound
+
+commit 8f9071b7d0a205b6dda40da28c358f1e26e007a0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:26:13 2019 +0000
+
+    add id to norm1
+
+commit e3197c61ce5de2cab4b36fe07b913c526844d328
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:24:54 2019 +0000
+
+    add id to stage1
+
+commit 3956a968ae847f27b3e46ff805dc75c259e1c544
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:22:19 2019 +0000
+
+    add id to stage0
+
+commit 074236f303578939f925f3668c88b7e6cd929c75
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:18:39 2019 +0000
+
+    add id to align
+
+commit 3597dda29683c1b06bd70edc882f4585f1243350
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 02:15:21 2019 +0000
+
+    add id to denorm
+
+commit ec47adc80a3c803553eff3a72fb454535512bc68
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Mar 5 00:58:31 2019 +0000
+
+    add id passthrough to specialcases class
+
+commit dce49005fc8ff964c7d5cb29f4add1399c983e20
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 23:41:18 2019 +0000
+
+    reorg special cases setup
+
+commit 28a369a5101917cc87cd79529875583d6a3950fb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 23:38:19 2019 +0000
+
+    add id_width to parameters
+
+commit 5d8f6a372abb7416e9188a3c187bfd8dc5e78f2f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 10:59:07 2019 +0000
+
+    remove unneeded code
+
+commit 6b442c377264b326fded1d99bda44d4d6c5aab42
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 10:57:08 2019 +0000
+
+    reorg setup functions in more add phases
+
+commit a6144caf8ee4c7d943f2e12fa3060317a3139986
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 06:03:48 2019 +0000
+
+    cleanup modules, however multi-cycle align needs to be like norm1
+
+commit 6f579a121660f7b8f117dec32d3c98011d2302fc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 05:39:06 2019 +0000
+
+    split out single-cycle normalisation to separate module
+
+commit 1f54946e9b8215d0a26228722ba42f4793325901
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 05:38:45 2019 +0000
+
+    enable single-cycle in FP16 test
+
+commit 3cf40e4f10930eceece3dacbacc54586def45c1f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 04:25:56 2019 +0000
+
+    single-shift normalisation right-shift: normalisation now a single-cycle phase
+
+commit 48c84a9dcb92896ed84cc29fa5202302b9218baa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 04:13:02 2019 +0000
+
+    use MultiShiftRMerge module instead of shift_down_multi function
+
+commit a4750a653a71017c4169fe0064bae6a700e6a463
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 02:34:35 2019 +0000
+
+    remove chain dependence, calculate ediffs in parallel with comparisons
+
+commit 2a3b9f8b3e32f0290cf23553d4079c9b4372a942
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 02:26:23 2019 +0000
+
+    comment out unneeded code for now
+
+commit 3aed7e16d3e76217043c181b189d23d0689e78b6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 02:25:56 2019 +0000
+
+    convert to only use one multi-shifter
+
+commit b006a58e3980bca9d34b26b2222eb0bdee0291c9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Mar 4 01:11:10 2019 +0000
+
+    rename stickybit variable
+
+commit 51a14e0cd1245876b065be25d463c8e6509d30df
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 23:13:51 2019 +0000
+
+    unit test for multi-bit shift right with merge (sticky bit)
+
+commit 64a580f407733a1eda89998db5999ad6940eef4a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 10:12:51 2019 +0000
+
+    cleanup
+
+commit 17b7ad3644de8b7f25af107b5de362fdcef373f7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 10:12:04 2019 +0000
+
+    small optimisation, move subtraction of -126 from exponent into FPNumBase module, use it there and in normalisation
+
+commit 430d629639b88792caf81d987ae8eb1f1b1d8fa0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 09:59:56 2019 +0000
+
+    add 3 extra unit tests
+
+commit b206b4ffb1a2221d5f3c388f8c6ecc97bf2606c6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 09:55:44 2019 +0000
+
+    limit count leading zeros to stop exponent shift-amount going below min exp
+
+commit 7cef607cae22586ffa4b376fc167fc668f59be14
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 09:52:54 2019 +0000
+
+    fix shift class syntax errors (untested)
+
+commit fd8e37e252263867c93c32fc416202d5182c7b00
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 02:34:20 2019 +0000
+
+    use priority encoder for normalisation in single cycle (done decrease)
+
+commit 5385346fc59bc79f549d90bbf69e5d753040c4be
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Mar 3 02:30:59 2019 +0000
+
+    add in FPNumShiftMultiRight class
+
+commit 06dfe62eb9776d94513d7fb5905be4cd6afc077f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 19:20:25 2019 +0000
+
+    use bool() function instead of reduce(or_)
+
+commit b83c33f8f0ddfee98a3b0de002e397eb01c5aecb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 18:02:20 2019 +0000
+
+    got single-cycle align working again (accidental combinatorial loop)
+
+commit 559a675c570f9373777426ee80cedc9fed13690f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 14:13:45 2019 +0000
+
+    turn FPOp into module
+
+commit a6e70cb6a24ebff8ca2b6fbc98c64c687523a9bc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 13:58:45 2019 +0000
+
+    move put_z to PutZ class
+
+commit 6bc62eadaf1dce099817bf559905f2b92ad70351
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 13:14:28 2019 +0000
+
+    reorg pack setup
+
+commit a69d282cacb21f94c0917cfc4e0dbcb353d7f70e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 13:12:30 2019 +0000
+
+    reorg corrections setup
+
+commit 0e7946f9994c09b5f6cfe6eb66e6af0031a45b4c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 13:10:29 2019 +0000
+
+    remove unneeded function call
+
+commit 40145a6a5b049197f1f12cd678a05a41c2600145
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 12:56:38 2019 +0000
+
+    remove global z as output from specialcases, use sc.out_z
+
+commit 514166890e793688c593162877f599c8cf298151
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 12:47:46 2019 +0000
+
+    remove unneeded variable, use module overflow to get rounding signal
+
+commit b8b05bcf55a80a3cdd6e01aaa215e3c6948e9711
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 12:42:30 2019 +0000
+
+    managed to make round signal an output from normalisation phase
+
+commit 0242003ad6948764f337df73329d76aaf6802bb7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 11:22:58 2019 +0000
+
+    tidyup, remove unneeded intermediate
+
+commit ad575d8ff4cd6ac374ec0df793841928ba4e0f36
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 11:22:26 2019 +0000
+
+    tidyup, remove unneeded intermediate
+
+commit e93d491f1aea8c0adea47f4cc51c162dfc0a7f77
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 11:18:56 2019 +0000
+
+    reorg FPRound move setup function
+
+commit 6778b58b01d81f8babfb1561041eeb866979fa9e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 11:16:05 2019 +0000
+
+    add comment about add0+add1 stages
+
+commit 0b09b0e015ef54c7c74387d98192b81cee215bbd
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 11:09:44 2019 +0000
+
+    add1 module setup reorg
+
+commit c3ff4a18ff2dfdd6fcbe07bb2aa2cba0fcd05b58
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 11:01:41 2019 +0000
+
+    remove temporary external z, use add0 output, connect as add1 input
+
+commit 2f7e6ad5cb0fe76652d9d4cd6025f48b19f98da6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 10:52:52 2019 +0000
+
+    reorg: move add0 setup function
+
+commit 3e074b3bc5123a3d615379d56c4d18874dbf3576
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 10:49:54 2019 +0000
+
+    use correct local output from pack chain
+
+commit cabe068ee5b0e4990af8906c54a9b42b251eb712
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 10:46:29 2019 +0000
+
+    reorganise normalisation init: move setup function from mod to class
+
+commit 7aa9d4daf355080961dfef3d4fdeae70ee784b82
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 04:00:38 2019 +0000
+
+    add module links (gives useful names)
+
+commit 6f985a00540c00c590e3bffa26b214cd74477bb5
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Mar 2 03:53:34 2019 +0000
+
+    complicated way to create a loop inside the normalisation module
+
+commit cebab15f305d2705943e5e8e6aa1dc660828bcc0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 22:47:31 2019 +0000
+
+    remove variable overflow
+
+commit 031369a527b2795212de74999128478b6c7face5
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 22:31:40 2019 +0000
+
+    connect corrections to pack without global z
+
+commit 402940efb369b6463f576d22a1329cbb8d9a84b3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 22:25:40 2019 +0000
+
+    split roundz from norm z
+
+commit 96a14ea216c0496f839b3a4186516bd515d6f3c6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 22:14:02 2019 +0000
+
+    pass add0 z through to add1 independently
+
+commit b36be752d9217be6623edf635e327e5fcc8a93b7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 21:34:49 2019 +0000
+
+    add new temporary z for result chain
+
+commit 03eff98a7a6dc04be2ad45344d6e079a6289cb5b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 13:23:34 2019 +0000
+
+    connect add1 to norm1 overflow without global store
+
+commit 73034bf3d2a5af53d2269d8dceebf04616ee32a0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 13:05:24 2019 +0000
+
+    merge normalise_1 and normalise_2 stages
+
+commit 5266edd6310043d3b99f8584a0d65742bd3670d9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 12:01:26 2019 +0000
+
+    commennt use of intermediates
+
+commit d5dbc25f2758491615624074679303040063c1df
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 11:26:39 2019 +0000
+
+    store zero-extended a and b in temp signals
+
+commit f06311995594afbb362c238f43e3dfa573c614e6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 11:20:18 2019 +0000
+
+    store tests in temp signals
+
+commit 00d8cebaaba8b44f649f21156f2aa851d997b9ea
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Mar 1 09:30:18 2019 +0000
+
+    experimenting with chaining Overflow module
+
+commit 3d0b7f7818a35c8284e45b9a32c2428e3adba7d0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 13:15:53 2019 +0000
+
+    use output from align as input to add0
+
+commit d36211df0eee2f878c97f533cd6e061b63765762
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 13:03:02 2019 +0000
+
+    remove commented-out code
+
+commit 34caed2a765f8380e9723cbd84741421a15b7465
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 13:02:18 2019 +0000
+
+    use GetOpMod for b
+
+commit 9bf1d5aa6c267ebac84f91b9328fa05908baae18
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 12:58:33 2019 +0000
+
+    create and use GetOp module
+
+commit 2c72bbaafc4e4ec55a4439f096a40e3d911cf599
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 04:42:13 2019 +0000
+
+    move fpnum_b to class FPGetB
+
+commit d3a98f8059ea45d4093957e38e9e56f1dbfc25da
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 03:43:05 2019 +0000
+
+    narrowing down rounding error to use of Norm1 module
+
+commit 1d9f17711b2b816f07ca3518ddcea612f23d0729
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 03:10:46 2019 +0000
+
+    separate denormalisation module and use it
+
+commit 5a1e9788c04b7ddeceb0cb709a6413da1a358a53
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 02:48:45 2019 +0000
+
+    use denorm exponent signal
+
+commit 628b86b268cef21f799f47b7c4a7f5a32c8d4c9c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 00:50:10 2019 +0000
+
+    sorting out unit tests, comply with IEEE754 on RISCV
+
+commit e209a4938625d7e0d43c4f477b824ef889999929
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 28 00:13:05 2019 +0000
+
+    recompiled sfpy, testing FP16 again
+
+commit 75d1c6da34bac478742a287f8e8e6783dce7cadc
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 23:09:06 2019 +0000
+
+    add Makefile patches to README
+
+commit 63aeeabaf9079b5bc648cedae1a243d85195a67b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 17:18:23 2019 +0000
+
+    whoops, overflow not right, reverting
+
+commit 5c757752c949da6db1684eeedfb58f23b90ac645
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 17:14:21 2019 +0000
+
+    add failed test
+
+commit 0aea70cc291d6ab896f33d80f2f1892ac1c5dff8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 17:14:17 2019 +0000
+
+    assign tests to signals
+
+commit 0e557669c53c1c7c0ee3ddbad3cf8bf151eeeb24
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 17:02:50 2019 +0000
+
+    create single and multi shift cycle, single doesnt work, multi does
+
+commit 34e5645ef036d6c545c112807d9d29599701e3e2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 15:34:32 2019 +0000
+
+    more chains between inputs and outputs
+
+commit 884a57f6ca458cdf0704f68be41fbb9ae0c275ab
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 15:24:18 2019 +0000
+
+    move of = Overflow() out of FPADD, use chain
+
+commit 53cf8aae6ffb355ce65a554e8987cb4fcb13c226
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 15:04:00 2019 +0000
+
+    remove tot from FPADD, use chain
+
+commit 8d5510e7181e1cec2a8f57e9d1625801e34d27c4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 13:58:51 2019 +0000
+
+    connect add0 to add1
+
+commit 43ad170c527b36cbe7f968feaacabb0de3d061e0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 13:56:31 2019 +0000
+
+    create add1 stage module and use it
+
+commit 59ac9d6289f3a45ec2d705adc494d48f21cf98e0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 13:30:36 2019 +0000
+
+    try some more chaining of inputs to outputs
+
+commit b832ccb1d4473c8c967e500493a28c3f232498a4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 13:21:22 2019 +0000
+
+    pass output from normalise_2 to input of roundz
+
+commit f5d86bd5e275785b798d477946831b4e47281b7c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 13:15:01 2019 +0000
+
+    create add0 stage module and use it
+
+commit d7b8cc01c5cf96424152812cb95044c017b995af
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 12:31:15 2019 +0000
+
+    name modules correctly
+
+commit faaf5021d71d92fd62ef8402b1f25b3a0be8a030
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 12:29:32 2019 +0000
+
+    whoops norm2 using norm1 mod
+
+commit 26471e1b679b7b2e9feffdca9e5258b3258c1406
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 12:26:16 2019 +0000
+
+    create normalise_2 module and use it
+
+commit 5dc0c2c2366eb9c51d25cf75fb9d6f6184bd7673
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 12:20:51 2019 +0000
+
+    put exponent > 126 logic in FPNumBase, use it in norm module
+
+commit e54f2c022828dd2e6a3f2bef011e0555cc5159e4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 12:15:34 2019 +0000
+
+    split out first stage normalisation to module and use it
+
+commit e0018a3337ee4582ab3eabeb57bee79bf067f4a7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 12:10:31 2019 +0000
+
+    reduce random case test numbers as well
+
+commit 626f7c38c3e5cee10ad185960b2bbda1233c0f0b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 11:47:15 2019 +0000
+
+    reduce number of unit test runs to get quicker more comprehensive coverage
+
+commit 18e958a59eb283112d9f134f4e7b1cfb7421dc57
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 11:46:54 2019 +0000
+
+    split special cases into separate module and use it
+
+commit 0310d8b65bc027d6072785b395a567149ba40c1a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 10:30:34 2019 +0000
+
+    create and use FPPack module
+
+commit 865757913bed95207c19debd632f94fd5b1b74cb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 10:13:50 2019 +0000
+
+    create and use corrections submodule
+
+commit bd8a1db591e70333a400543cc2225c7b7f2fea6c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 10:04:06 2019 +0000
+
+    rounding done in module
+
+commit 52b5af9b4d08920bb9d5284644e82df4f1012ef7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 08:07:54 2019 +0000
+
+    get roundz state to put answer in explicit output, sync it to z afterwards
+
+commit 7cbd033401d511e83145d91ce0061eb2d750e9c8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 00:29:50 2019 +0000
+
+    clean up unit_test_single get_case based on how dual_add works
+
+commit 262f37d15b93a473d8de4b31c0297bb130473bfd
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 27 00:12:27 2019 +0000
+
+    clear STB immediately after setting, stops add1 repeating computation
+
+commit 370ce3f6040fc62df2121a87328f6fdb44f75344
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 26 22:28:56 2019 +0000
+
+    moving internal strobe test forward is ok
+
+commit 480f720419c71a37c10ae78d28832f9757d74e91
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 25 08:15:57 2019 +0000
+
+    invert stb/ack between add1 and add2
+
+commit 50dbc469179f0d8bf310f2cf180b17be0ea1c650
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 24 09:27:30 2019 +0000
+
+    experimenting with dual add
+
+commit 6fed7002a094e27c85b2e74da887184d2bf08a0b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 12:57:26 2019 +0000
+
+    trying different testing for 2nd round
+
+commit c9caca5583aa11c10adf0902c0546e4c25b7d681
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 12:40:41 2019 +0000
+
+    use function to get chain of v/ack/stb
+
+commit 6487a34301595940debf733c6c0a7053fd30cefb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 12:33:31 2019 +0000
+
+    yippee got dual add chained together
+
+commit d1403516711e59fbc3860e51537f329549633d3b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 12:22:10 2019 +0000
+
+    whoops revert decode inside module FPNumIn, causing problems
+
+commit c4262e79c251db057cf49dbd2c753f3319b2ec25
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 11:56:58 2019 +0000
+
+    add dual unit test
+
+commit 15294360273b7610bc6c12584c82cd20651f6707
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 11:56:28 2019 +0000
+
+    move unit test order
+
+commit 0a433b8e6218ae36331aeb00ece4b004af00bdad
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 11:56:14 2019 +0000
+
+    remove unneeded class declaration
+
+commit d30f87d788f953fdac4db971da41d3d09cfc6807
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 11:30:44 2019 +0000
+
+    add a dual-chained add experiment
+
+commit 978906052a938cb8c6f0056d1f0395a18e6acaf8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 23 08:43:58 2019 +0000
+
+    store logic-test conditions in intermediates
+
+commit 46c346c523cf0a94f3f1b3060f139058a9539fd4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:55:44 2019 +0000
+
+    isolate inputs and outputs in FPGetA class
+
+commit 56797e67ce0f6150c3e55c4885959be6dbf4f3e7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:19:31 2019 +0000
+
+    FPADD need no longer be derived from FPBase
+
+commit 5dd4d809198de2ae03605173bfcf2c731be3474d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:18:15 2019 +0000
+
+    remove explicit code-adding of states, use for-loop instead
+
+commit 424780b0cb60d5ab487fef877b1fc469afa6841c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:13:14 2019 +0000
+
+    move putz to separate class
+
+commit 5b3fef624ed9a409a7c12a799153ab706b91dcc8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:11:53 2019 +0000
+
+    move pack to separate class
+
+commit 0932162242f7e77f8f8622eb0b03ceff1d332e73
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:10:41 2019 +0000
+
+    move corrections to separate class
+
+commit c9601b52ffa461d1eb6636d6d55e595733eef38d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 10:08:37 2019 +0000
+
+    move rounding to separate class
+
+commit b7595d8af6e1634e08dd7bca03f0ced228d7034d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 09:38:14 2019 +0000
+
+    move normalisation stages to separate classes
+
+commit 86a5fecd6baf56e431ae25502e8643ff68ccd573
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 09:27:49 2019 +0000
+
+    move add1 stage to separate class
+
+commit c21e755b12a7c7c12bf6cfd1f420b19e7bd8ecde
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 09:23:12 2019 +0000
+
+    add comment
+
+commit c7fea07d7328f7c144effdcbe8ce22352029d811
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 09:22:24 2019 +0000
+
+    split out add0 stage into separate class
+
+commit 4f274ca83d81bf1baa7002c2f5af89c2df3a91b7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 09:14:22 2019 +0000
+
+    move align to separate class
+
+commit 243ee0ba3850621d9cbb5d9f70ff1dfee04cad87
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 09:10:07 2019 +0000
+
+    create separate denormalisation class
+
+commit 20730a5c9556d5e35a21f71583a0b514f2dfb739
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 08:52:12 2019 +0000
+
+    move special cases to separate state class
+
+commit e1859a9abdb55c218b2272609a05750c11ab8634
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 21 08:45:33 2019 +0000
+
+    move get_a and get_b to their own classes
+
+commit d6e5544bcacbaca4934a63706892c042c01c3db7
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Wed Feb 20 18:50:07 2019 +0100
+
+    Remove coments with verilog code
+
+commit 78e77428174cfafa67b0f67e2db5a5a20e54ce75
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 05:24:06 2019 +0000
+
+    split denormalisation to separate state
+
+commit cf05c428f2442b1432e2dfdc32f93c5db66cba44
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 04:54:41 2019 +0000
+
+    latch into FPNumIn within module
+
+commit ad854557f228ce234a0bfa41e8b315f2a54f8f4d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 04:26:31 2019 +0000
+
+    create separate modules for fpnum in and out
+
+commit 6d1c948b67f7155ab63475032b38ea5e3fdb99e3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 02:52:10 2019 +0000
+
+    make module out of overflow class
+
+commit 39be660b8a61d2af1348f4fedf507f2c492529c4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 02:30:03 2019 +0000
+
+    create module for FPNum
+
+commit b2cc0192847d019a30d7f760a1ffb71319f4935b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 02:17:33 2019 +0000
+
+    reset allowed on FPop, not on FPNum
+
+commit 606bf9eb6eba1ff0cbb2afcaa0a3d05c07f43bf2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 20 00:45:56 2019 +0000
+
+    store roundz test in comb variable
+
+commit 468cb689dc4e797c17065e7f882b936791420afa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 15:52:13 2019 +0000
+
+    store testing of nan/inf/zero in comb Signals
+
+commit 1ad14c0abd7e4fb79d0d45b8ae2d9248d0d8d7b9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 15:51:20 2019 +0000
+
+    move setting of stb into else block
+
+commit 06b5f4ac3d397ae96402169c23fdb1bf7eba4c30
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 15:27:12 2019 +0000
+
+    reset_less on signals that do not need it
+
+commit d26d9dd46e9fd22a1f89357a6fbcecf0eb723f44
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 12:51:50 2019 +0000
+
+    reorganise unit test single to do much more comprehensive test cases.
+    
+    specific edge cases on the exponent are covered, with random mantissas:
+    -126, -127, 127, 128
+
+commit ee00fd20e0d3717ac32227c6ecad308ede7d99e5
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 11:23:22 2019 +0000
+
+    take out FP16 non-canonical NaN weirdness for now
+
+commit 9d56131f85e79434877858c4d4447151b6c54f4e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 09:20:13 2019 +0000
+
+    add corner-cases +/-0 + NaN
+
+commit 1105e1d4c6903edcde553a3bc190978fb8420e77
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 08:24:20 2019 +0000
+
+    add FP16 add unit test
+
+commit 5371cd400205c92593911ff94b4d5e050634bd5c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 08:23:20 2019 +0000
+
+    INF + -INF bug
+
+commit 5c0058aba5b26ccf44564b4cc490a08323786983
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 08:05:29 2019 +0000
+
+    whoops FP16 mantissa off-by-one
+
+commit d4a692ce3c03f415d625ad9ffc05218db442e9b6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 07:41:35 2019 +0000
+
+    remove hard-coded width
+
+commit c1e1bae5f4546aa2343a1b3238cc6d384dbed7f2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 07:41:23 2019 +0000
+
+    add FP16 format
+
+commit 223916b7bb72d4dc241c8fa275b6e1db173c01fe
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 06:41:50 2019 +0000
+
+    add shift up multi function
+
+commit 1bdd112da4fcfd5eac2d906e39c7802bff55f145
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 05:41:28 2019 +0000
+
+    add extra regression tests (a + -a) for add
+
+commit 47115959f204429fdbe22446e40b64ae6c6a79be
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Tue Feb 19 05:39:14 2019 +0000
+
+    comment for a + -a special case add
+
+commit 23e796da73962b32b5513d975446fa89dfabaca0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:32:38 2019 +0000
+
+    add 64 bit mul unit test
+
+commit 61b2d414a758e3ba146988f197311e510a1c1b97
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:32:20 2019 +0000
+
+    whoops, off-by-one in use of mw, in multiply_1 stage
+
+commit af56c28dd6b44f60eee106d8bd902314676b9381
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:26:52 2019 +0000
+
+    whoops, messing up on m_width *sigh*
+
+commit 4c3686c20c54004cfb96baf825d4c475a4f39a52
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:23:52 2019 +0000
+
+    use double run_corner_cases function in add unit test
+
+commit 6632e5ac2f86a4dd7b43b5951802774f14145711
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:22:57 2019 +0000
+
+    add corner case unit test function
+
+commit 66cb3b90e9337d28936849ae937e5507ee4ca54f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:21:52 2019 +0000
+
+    doh! use z mantissa width to specify product width.
+    also take out hard-coded numbers, ready for 64 bit
+
+commit 1c58ae1a0dfee9150ba23d3ff8a997e463cc5eb0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:16:08 2019 +0000
+
+    use common run_corner_cases function
+
+commit b4a06a1ee88e2c143a3f29e8a6331b23c36ca9b9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:15:03 2019 +0000
+
+    use common run_corner_cases function
+
+commit 0fc3bbc63935663feb4d9c2926dabaf9168e26b0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:13:31 2019 +0000
+
+    add mul unit test
+
+commit b1e75f684543b121fd25635e9c393c25331c5037
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:13:04 2019 +0000
+
+    special cases, sign of zero and inf matters: a.s ^ b.s
+
+commit a62c8c5881b2aa0054a0fa14eeae8723f92cb846
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:12:16 2019 +0000
+
+    missed indentation of if statements in special cases
+
+commit c530bcd516416b79cc3c98ba6884ef62e0731084
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:11:47 2019 +0000
+
+    of.guard, of.round, of.sticky - of is a class with members "guard, round etc"
+
+commit 430c6b2865abf24a9585bd44017cb06562a4d5df
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:10:28 2019 +0000
+
+    m.next not m.next +=
+
+commit 6315df2ddb2771be3ab41bbf6d943df087851241
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:10:07 2019 +0000
+
+    whoops, self.width not self.m_width
+
+commit 268fcd9d5ea8cd741d6078a54f99c01d78fd850f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 21:04:29 2019 +0000
+
+    add corner case unit test function
+
+commit ec4eb0b3ffee9239d043e1ad2f8c34475670abcb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:22:50 2019 +0000
+
+    diff on div and mul shows corrections stage missed out
+
+commit db2140abde0b7cb784f5435f21498902fecbb661
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:20:51 2019 +0000
+
+    use get_op functions, easier to do
+
+commit 924c3fee2f21440de0fb11b30068c85a5db80a9a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:18:48 2019 +0000
+
+    product in multiply, not tot (was from add)
+
+commit b2b09924d249294b3a5523aa3f0105aae4d0f3bd
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:12:24 2019 +0000
+
+    corrections in whitespace due to use of tabs
+
+commit 59953a0d29ab7ab1dc4e293e51378c21797f5f50
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:08:14 2019 +0000
+
+    mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False
+
+commit ba5101dcf4cb0b553685a262476dced55b67ea51
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:06:51 2019 +0000
+
+    add requirements (dependencies)
+
+commit 7f67c091fe045b9e6f304a718486b8c936235aaf
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 18:05:38 2019 +0000
+
+    quite a lot of corrections to div special cases
+
+commit a9441a2d5af3bfbf135d46c2d95cd0129bcc3e4a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:43:13 2019 +0000
+
+    add regression test on div
+
+commit ad762e2e795b32191b5fce237771a209e0373d88
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:42:59 2019 +0000
+
+    remove zeroing bugfix correction, not needed any more
+
+commit 0a011e052efcd87791dcdc5e99cac9122f68418c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:37:52 2019 +0000
+
+    split out edge cases from unit tests into common files
+
+commit 927778d06a1b86539512186ee66bf44ac6485203
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:30:25 2019 +0000
+
+    add operator argument to unit tests
+
+commit 4388bc894114ed31ad1f3bf671a02ce7768c82e8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:22:07 2019 +0000
+
+    add div unit tests
+
+commit d806377a3656d69c3497c2ab9ff69e6c0e7bc5f4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:17:19 2019 +0000
+
+    split out common double-precision unit test code
+
+commit 34bd8c71bd35df7e2c35e1ee0fcafeefb92cb67c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:16:21 2019 +0000
+
+    split out common double-precision unit test code
+
+commit 89263ca04fdbda2bc30a8476eb6e3b119551da87
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:15:33 2019 +0000
+
+    split out common unit test code
+
+commit 1ebd806f70134eb4c96d6334c01d3691b6f4e014
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:13:07 2019 +0000
+
+    split out unit test common code
+
+commit 2ed303b3a16a1a7f23c3105c41ffae680119cde7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 17:12:44 2019 +0000
+
+    whoops wrong gitignore path
+
+commit fb29a5a984339759f4490447dab079a5f10e7b8f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 14:45:48 2019 +0000
+
+    add jon dawson add64 unit tests
+
+commit 4d0c20ae40360f5b4d0215d459a24e64d580cdf2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 12:20:29 2019 +0000
+
+    add comment for random number tests
+
+commit e41ed2689503aece121121c78171f696294bdd37
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 12:08:55 2019 +0000
+
+    test case fail, 2 numbers exceeded -INF but +ve INF was returned
+
+commit d30d28fd7c323582d79cf949fcd865d187fb9b9d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 12:05:26 2019 +0000
+
+    whoops set mantissa = -127 instead of exponent... oops...
+
+commit 308221724c16d6413ffd674eaeb92347d503b5c3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 11:56:18 2019 +0000
+
+    fix unit test use of xrange, replace with range
+
+commit 40e7f99d07484253630d09a339547f2db1ddd4ce
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 11:55:33 2019 +0000
+
+    fix a - b = zero by adding special case
+
+commit 4c62da6b74c69264380985d3041f5a81d52e562b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 11:27:03 2019 +0000
+
+    add unit tests
+
+commit 859050716c15df1981067e8ac0568ac860660d41
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 07:00:56 2019 +0000
+
+    use straight << and >> operator instead of multi-level Mux
+
+commit 791fa8e2e604d862a83ae18100f09b0f52bf01e7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 18 05:24:49 2019 +0000
+
+    add .gitignore
+
+commit f24963b0d3a0a9b7efd937258d0e95ee2011a8a0
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 19:05:41 2019 +0100
+
+    Finished the module states and added __main__
+
+commit e1db3d985344622c4782ec9c4f126995e2b795de
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 18:43:24 2019 +0100
+
+    Add more special cases to the module
+
+commit ee15ea9d3218838e9c2fd932317838118d42a883
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 16:40:24 2019 +0100
+
+    Added comment to explain a case
+
+commit e82a1942a48def173f8d3e3d4cdf67195482ecef
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 16:36:51 2019 +0100
+
+    Translated more of the special cases to nmigen
+
+commit ad64a2b559a9290aa97693c3f0391acfaf865a87
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 16:27:52 2019 +0100
+
+    Translated some of the special cases to nmigen
+
+commit 84e7d8bd75b84dba580973be2da5d527e4b148d3
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 16:11:08 2019 +0100
+
+    Started to build module using functions instead plain translation from verilog to nmigen
+
+commit c832b3bb72c5855b2c413ee3abef910a4e6eca45
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 16:00:29 2019 +0100
+
+    Started to translate special cases
+
+commit 04421658bac4d2443b6b226726841132730c6806
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sun Feb 17 15:42:22 2019 +0100
+
+    Done unpack in nmigen
+
+commit 0f8a559a09d8f5133e0eec3303fccb7ea5361bd7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 14:08:58 2019 +0000
+
+    add unit tests that push the mantissa to zero or close to zero
+
+commit 20efd9f948e67d17b3718bb4c4a6b9175ab8aadb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 14:07:33 2019 +0000
+
+    add TODO comment
+
+commit 9ed736e718dfd511f0c68896d3e3dc1c78402cb6
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 14:03:29 2019 +0000
+
+    test single-cycle align phase on 64-bit add
+
+commit dd27268b20a9d64caa5e3bc07f702982dc8d63c7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 13:09:55 2019 +0000
+
+    add single-cycle version of alignment process in fadd
+
+commit 0b07ec425f1742ce338e977652db4fecc6f8f191
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 13:07:06 2019 +0000
+
+    add a variable-length single-cycle shift_down of mantissa, and unit test
+
+commit c151716c38ad3a8a545f8e4193cdbc2c9d5e35ee
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 10:03:51 2019 +0000
+
+    add a MultiShift class for generating single-cycle bit-shifters
+
+commit 688f4f6f6ce0737c05cda16bcaab6cf7d8ee72cb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 08:22:03 2019 +0000
+
+    add extra comments
+
+commit aa66b492fd25d9750ad331eb9ffdc6f80ae342ee
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 07:42:23 2019 +0000
+
+    add double-width divide as well, and preliminary unit test
+
+commit f68605ababcf961defbcf83005dff4699f83d373
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 07:16:22 2019 +0000
+
+    add beginning unit tests for 64-bit add
+
+commit 258b33ecb3853122ea29ec4c66936f19f5943138
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sun Feb 17 06:42:21 2019 +0000
+
+    convert to more general base classes, start support for FP64
+
+commit d6b8036d20ce202d94ae862ecacaa20b306057fe
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 17:19:28 2019 +0000
+
+    add extra random div unit test cases
+
+commit 06bf724fefa6abc3e76fac77ebd095a1fe13294b
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 12:29:24 2019 +0000
+
+    add another random div test
+
+commit d85cc8830fe155ca83b2e81b95d3e4379da94baf
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 12:25:36 2019 +0000
+
+    comment divisor stages
+
+commit d9a754109b2902e62868038e460713e103b5c3cf
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 12:22:12 2019 +0000
+
+    rename (shorten) divisor variable names (and comment them)
+
+commit 60861482dcda7f752cc17477e993df063d9f2c79
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 12:14:21 2019 +0000
+
+    add extra arbitrary div unit test
+
+commit 2b07cf40c9d3de3b48e10d07b04615307bdf332c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 12:13:06 2019 +0000
+
+    correct comments
+
+commit 8d492f5eec29ba2910f4d250dca70fa08f4170df
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 12:10:49 2019 +0000
+
+    first initial success with div algorithm
+
+commit 11688f2114181c0ced5e041cb6841fd8419a6a5a
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sat Feb 16 12:34:59 2019 +0100
+
+    Fixed typo in get_b state
+
+commit 06a93cddd0ae1af04538d471f66136c8d9c50062
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sat Feb 16 12:34:17 2019 +0100
+
+    Did get_b state in nmigen
+
+commit 495d64c21b1e949b544b1d0eb3f7412e7ab23109
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sat Feb 16 12:27:29 2019 +0100
+
+    Did get_a state in nmigen
+
+commit f4edcebbd1b2ac9ecdc55e53ccd7e80c369db23e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 11:25:15 2019 +0000
+
+    remove some test cases from div
+
+commit 0611568bd02236421ea892e81cddd857e38a2978
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 11:24:12 2019 +0000
+
+    add div experiment
+
+commit a731173a2bae14fbf339aea511b066ddf58aa8a0
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Sat Feb 16 12:11:41 2019 +0100
+
+    Made a file and started to do porting from verilog to nmigen
+
+commit f2df35e4b4d6476d929389fa4dbeaed986deedf5
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 11:03:28 2019 +0000
+
+    op_normalise does not need overflow class arg
+
+commit 91fa69f581e94e0b62f1fb69a158f824ee06299e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 10:51:06 2019 +0000
+
+    split out base classes into separate fpbase module
+
+commit b5819d705aa1b840221ccd7a8045a614a694947f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 10:48:47 2019 +0000
+
+    add op_normalise function
+
+commit aeb0c772885d60535ed20f09449092ae837c42ee
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 10:45:41 2019 +0000
+
+    pad with zeros if needed in decode
+
+commit b6803d366abaab2533647de4b0f569bea2c6750f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:47:55 2019 +0000
+
+    separate common functions into FPBase class
+
+commit 69e3e86a50ca7295268a0fa9bc97216cabe1896c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:45:25 2019 +0000
+
+    move denormalisation to function
+
+commit ae85fc94757455bb8cf44a8ecd410dfba35ec64e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:41:49 2019 +0000
+
+    add comment on special operations
+
+commit c4294073c4b379bfe406a36e91fc264aad6f4b32
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:39:49 2019 +0000
+
+    whitespace cleanup and more comments
+
+commit 0c7bb8e4e82b58d122229c2344eb8ff923ae4784
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:32:26 2019 +0000
+
+    get rid of unpack phase by making it part of the get_op
+
+commit 5e8129603bfdcaab465c76dc23f1a9f939977b43
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:27:54 2019 +0000
+
+    comment functions
+
+commit 60a2a4dbf9dc2a50ed54884127177fae1e53637f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:15:47 2019 +0000
+
+    rename round function to roundz (round is a keyword)
+
+commit 4f73a467f1f3a9bd23a393ab783ca95b5b30ef3e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:14:26 2019 +0000
+
+    create put_z function
+
+commit f907216922d0880430f5a5435a9b86144dfe2a32
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:12:22 2019 +0000
+
+    create pack function
+
+commit 5107bbe121ee49a600b48f6467502a69a29d1df4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:12:14 2019 +0000
+
+    create pack function
+
+commit 20a9b26e19454870baec6db9fb9e82d0987df560
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:07:13 2019 +0000
+
+    move round to function
+
+commit e9ef7709bf7955693ab4c9ed74e87f81f4f45632
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:05:53 2019 +0000
+
+    move normalise_2 to function
+
+commit 85434e97dd06b23decca617612c77d75d10bb7ed
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:04:44 2019 +0000
+
+    use normalize_1 function
+
+commit 2476c8fc80e8007d643fdbd75536d5d5048ce8c9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:03:33 2019 +0000
+
+    move round, guard and sticky to separate clas
+
+commit bb86ad410e26c25ab9101a5ba4d4a0004d1cddf5
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 09:01:43 2019 +0000
+
+    add normalise_1 function
+
+commit dc7ec4300aa575b56412a6da68974a27245b8eec
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 08:55:09 2019 +0000
+
+    use get_op for get_b state too
+
+commit bc07e0680fb8dad61471ffe5b8a66a1d83688747
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 08:54:33 2019 +0000
+
+    create get_op function
+
+commit d9b1bf93a9a18746f103210ace6fa592cd8c3fde
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 08:48:21 2019 +0000
+
+    move value, ack and stb to separate convenience class
+
+commit b81949f4a5b04a66565b1fdc7a1125216702ca58
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 08:39:25 2019 +0000
+
+    use slice magic constants
+
+commit b6ff4584535f0c74ac29cba23c175271075a7806
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 08:36:41 2019 +0000
+
+    re-enable commented-out tests
+
+commit f72c2afee9e4fd69ef63124bb5ce44e72eff4664
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 07:54:04 2019 +0000
+
+    update README
+
+commit 0262bcdb0dd867807f133605a4910f223cffbfb8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 07:40:16 2019 +0000
+
+    remove unneeded import
+
+commit 07e16a2fcaa862cef2f01889e2c93493226e3ae9
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 07:37:27 2019 +0000
+
+    whitespace
+
+commit c2c01f96fcde637744e0490648f2f17956f82655
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 07:35:51 2019 +0000
+
+    no real point adding reset for internal pipeline variables
+
+commit 48dd87dd2ec6c5f6f6ef16a86bbe39a2f66496da
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Sat Feb 16 07:02:06 2019 +0000
+
+    add pipeline class and example
+
+commit 064541e8f20feb40216043bcdd211ffe192c6750
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 15:47:02 2019 +0000
+
+    more arbitrary unit tests
+
+commit 2356710243dd4361af2c2c17edc609eacf82ed61
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 13:19:16 2019 +0000
+
+    use constant P128 instead of 128
+
+commit ae1dc08c3e03c5f333c5d8af726ff59757454d48
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 13:19:03 2019 +0000
+
+    add extra unit tests (infinity / NaN)
+
+commit b82a84091dc232a5cfa675e7489978ac0a66d2f0
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 12:58:29 2019 +0000
+
+    add extra unit tests
+
+commit 1789c5892cb4ad8f4641bba426e857fcfe663854
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 12:51:42 2019 +0000
+
+    add extra unit tests
+
+commit 72f0c122d8fc7f0fc535deebd2d6d076b3a4f2e1
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 11:55:12 2019 +0000
+
+    corrections to shift_down and is_overflow, test "1.0 + 2.0 == 3.0" works
+
+commit dadb08c6930ec215f774062aee63ec9521819ce2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 11:15:01 2019 +0000
+
+    lots and lots of debugging corrections...
+
+commit 2716ffa5e594d7a993218ab45aa9534df3cac201
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 09:28:29 2019 +0000
+
+    improve assertion output for unit test
+
+commit e5c82b7a6b4802ea22bddd2d9d26e04f9ba7aafa
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 09:26:24 2019 +0000
+
+    add simulation test code
+
+commit 74bab3d18c99001537fdbcbe44a3dbf45027cd66
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Fri Feb 15 09:26:07 2019 +0000
+
+    corrections from running simulation
+
+commit a710a0d7956529e200ec9198314ef71ca1522b12
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 15:13:13 2019 +0000
+
+    add verilog conversion (commented out)
+
+commit 30392515cf6c026ffaeb6f00f4bc8773d354cbc8
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 15:10:44 2019 +0000
+
+    corrections
+
+commit 83486d7e84c2f9c97c1567c6524ff9e1890f67de
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 14:59:14 2019 +0000
+
+    remove verilog
+
+commit 9f0aa878789ad928e8b531fceb6aba606cc72c1a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 14:49:17 2019 +0000
+
+    corrections, out_z_* and friends are members of class
+
+commit 6b64076c86bc57550688ec1c74f59c29de6f3a97
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 14:46:19 2019 +0000
+
+    add in a "corrections" stage, small rework, split pack stage
+
+commit 0afb5e8aee35febe485ae89eddea2292c79685a1
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 15:37:57 2019 +0100
+
+    Translate put_z verilog case into nmigen
+
+commit 5113de1faa5b5d80f321dea5736b9fcc5806b3be
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 14:26:11 2019 +0000
+
+    add and use is_overflowed function
+
+commit a3ce022d1326033d2d0b6322481c0777af6c71eb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 14:09:19 2019 +0000
+
+    cleanup
+
+commit 80580ea474b77c136f7e588e8dc673407e56a99d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 14:06:31 2019 +0000
+
+    document guard/round/sticky and tot
+
+commit d7b21357824af961b0965076851bffe2474921ec
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 15:03:08 2019 +0100
+
+    Translate case from verilog to nmigen
+
+commit 99d1c6b9ff455df4c4888de0259db4956809ee8e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 12:52:48 2019 +0000
+
+    add code comments
+
+commit 486d6745fad6f8e16fd9e418847f8ca82a8ea453
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 12:47:12 2019 +0000
+
+    add set-to-zero function
+
+commit 7a596346d426eb2dac0110759e5d1842ec76340f
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 12:47:01 2019 +0000
+
+    fix bug in nan/inf, exp-bias needed subtracting
+
+commit 82de8d38c838bcffb494b06336533d1e795cb453
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 12:46:03 2019 +0000
+
+    add FPNum comment
+
+commit 05601351b3e542d91d4f6805810d1e4d53cd7deb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 11:35:06 2019 +0000
+
+    add comments for aleksander
+
+commit bfe16ca26c3a341fec771f634eee82eabbed5437
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 11:34:24 2019 +0000
+
+    add comments for aleksander
+
+commit a68eacb51223b30fe9f0513204a165ba6b12bff7
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 11:22:46 2019 +0000
+
+    use negative slice (now works)
+
+commit ec792e6838b139c3f479b3a3ede151cabd8ba519
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 11:09:59 2019 +0000
+
+    remove a_s/b_s/z_s
+
+commit 82a1f010c5c500a8c9215cba5dc7971bd92da118
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 11:09:43 2019 +0000
+
+    move align down-shift to separate function
+
+commit c98a9a9dcbfc94c6fe6262580432f74d89dd1ad2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:53:14 2019 +0000
+
+    move +127 for exponent bias into FPNum.create
+
+commit 6949ffef0414a8cff2d9e14857f627a91e449319
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:51:45 2019 +0000
+
+    remove unneeded code
+
+commit 487c5fac81adb9eb8d616295a6facdbc459f135e
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:51:28 2019 +0000
+
+    comments
+
+commit f4ba4287e22046c8366b6138ee8a9bf9cecb07d4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:48:07 2019 +0000
+
+    add zero, nan and inf checks
+
+commit 5e1a88814def18d3d7f3241363f335d2a82d20f2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:43:01 2019 +0000
+
+    create and use decode function
+
+commit 4cacba615bf4ec046fb3b87b2b190e40df65a28d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:37:43 2019 +0000
+
+    move create, inf and nan to FPNum class
+
+commit 11c9a7a4197619acd67405c51a098704bc51c6bf
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 10:35:13 2019 +0000
+
+    create FPNum class
+
+commit 6ca7b00bf57ffb3cb96b8b3c290057db009cd752
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 09:48:40 2019 +0000
+
+    add rounding stage
+
+commit dbb871d5dc6073145aa724c86cd584b63242a7eb
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 09:42:00 2019 +0000
+
+    add comments
+
+commit 3c50fb77c68d277ebc9592f448051bdd20beb469
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 09:38:09 2019 +0000
+
+    add normalise_1 stage
+
+commit d6b562fb042766004cf32088104211c55208554a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 09:22:04 2019 +0000
+
+    add NaN and INF functions
+
+commit 963a0c629d8558e447c2428f793b7b2937901a53
+Merge: 362b54b 52e421e
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 10:17:13 2019 +0100
+
+    Merge branch 'master' of ssh://libre-riscv.org:922/ieee754fpu
+
+commit 362b54b6e73894ccca070f53cee4b5817cf3b47f
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 10:16:54 2019 +0100
+
+    Turned the normalise_2 verilog state into nmigen
+
+commit 52e421e91ba1734cd95674c0bbf38dde638a510d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 09:15:47 2019 +0000
+
+    use function "create_z" which... well... creates a result from (s,e,m)
+
+commit 4884f6fae51c126c07eb49300b61ea0ef8fec15d
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 09:05:21 2019 +0000
+
+    add in comments on add 2nd stage
+
+commit 0d03803dd8fa042b2aa5d5cf412f8ae41c9ae261
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 08:56:39 2019 +0000
+
+    off-by-one in slices
+
+commit 32f9b3a0ea183ee193f804c946a8ef56c0d97eba
+Merge: 9d3ef49 83d0325
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 09:53:36 2019 +0100
+
+    Merge branch 'master' of ssh://libre-riscv.org:922/ieee754fpu
+
+commit 9d3ef49cdd08c4ffb9c82063857bc918a2add954
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 09:53:21 2019 +0100
+
+    Turned the add_1 verilog state into nmigen
+
+commit 83d0325f6318204db17f7a3edae5429cc588e8d3
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 08:51:18 2019 +0000
+
+    corrections on compile
+
+commit 0cb5bcb2f90da200924108bbe2b2ba0e598a1248
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 08:49:48 2019 +0000
+
+    add align phase
+
+commit 749109f2e5caf92367a70587f54555ef5913e454
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 08:38:57 2019 +0000
+
+    whoops accidentally indented too far
+
+commit 4d34c747aad8cff48a6f0ef0ef4c6380d08bcae4
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 08:36:46 2019 +0000
+
+    add code comments
+
+commit b122b5740d630b5348ab2c63c911e840b6053807
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 08:32:13 2019 +0000
+
+    reformat / indent add_0 stage
+
+commit 27144dd663214de35c5f97f8cca3396401d470d0
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Thu Feb 14 09:23:17 2019 +0100
+
+    Turned the add_0 verilog state into nmigen
+
+commit 3bdb8bf118d526d896fe72708c739fbb6212cbb2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:52:28 2019 +0000
+
+    add zero and denormalised checks
+
+commit e47b0a419e9640695c3d3c5923ab51e6f1b63942
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:40:29 2019 +0000
+
+    add special case, b when a is zero
+
+commit 541f086f5ba7e8d1084f1eae66a18bc5f4233bef
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:26:25 2019 +0000
+
+    add b inf special case
+
+commit 29cbeef4ef6b9a289a8a192cc735778e2ec11c3c
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:24:12 2019 +0000
+
+    cleanup and comments
+
+commit 0f623094c1018cbaf0945bafa043af3f6e67bc00
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:20:23 2019 +0000
+
+    add inf special case
+
+commit efae2c37edf8dd8670b382b3802a323c72517e71
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:13:15 2019 +0000
+
+    whitespace (indent)
+
+commit e5987629000197e645730a39ac1f51bc24e88cfd
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 06:12:44 2019 +0000
+
+    add first of special_cases
+
+commit 4ccb4d59bd50c5d5bff9008dac0ca034fc2d8e9a
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 04:32:09 2019 +0000
+
+    invert Cat order, use 3 zeros (3 bits)
+
+commit 7fe4616cc217cc2b8bf5243f931498d51965ad44
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 04:16:14 2019 +0000
+
+    spelling correction
+
+commit 357cf56e4ba03e2a0a1d54eb302678217e08d6f2
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Thu Feb 14 04:14:40 2019 +0000
+
+    corrected syntax for unpack block
+
+commit 5ee0dbbcec0a4c9c00d59362c5839926c3b933b7
+Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
+Date:   Wed Feb 13 17:20:49 2019 +0100
+
+    Replicated unpack part of always block into nmigen
+
+commit 9afc4398daac6380186715fe902512f661558c63
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Wed Feb 13 11:26:22 2019 +0000
+
+    add experiment
+
+commit 03d20ef6c3a8a178118ab29e14e21bc9fbec89c5
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 4 00:28:04 2019 +0000
+
+    add git submodule init to Makefile
+
+commit 5248a092891e80c5699fb5a54ef0f95595fbf784
+Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date:   Mon Feb 4 00:20:55 2019 +0000
+
+    added berkeley softfloat library submodule
diff --git a/src/add/fmul.py b/src/add/fmul.py
index 130d49e8..8e928bb7 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -2,7 +2,8 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState
+from nmigen_add_experiment import FPState, FPGetOp
+
 
 class FPMUL(FPBase):
 
-- 
2.30.2