From dc8afbaa21c7e471ecddeecf5efa18d2c358e1df Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 6 Sep 2020 12:11:25 +0100 Subject: [PATCH] add DEC/TB SPRs to spr pipeline --- src/soc/fu/spr/main_stage.py | 12 ++++++++++++ src/soc/fu/spr/pipe_data.py | 2 ++ 2 files changed, 14 insertions(+) diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py index de1ab2f2..b1262795 100644 --- a/src/soc/fu/spr/main_stage.py +++ b/src/soc/fu/spr/main_stage.py @@ -36,6 +36,7 @@ class SPRMainStage(PipeModBase): so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1 + state_i, state_o = self.i.state, self.o.state # take copy of D-Form TO field x_fields = self.fields.FormXFX @@ -65,6 +66,11 @@ class SPRMainStage(PipeModBase): comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']]) comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']]) comb += ca_o.ok.eq(1) + # STATE SPRs (dec, tb) + with m.Case(SPR.DEC): + comb += state_o.data.eq(a_i) + comb += state_o.ok.eq(1) + # slow SPRs TODO # move from SPRs @@ -88,6 +94,12 @@ class SPRMainStage(PipeModBase): # carry comb += o[63-XER_bits['CA']].eq(ca_i[0]) comb += o[63-XER_bits['CA32']].eq(ca_i[1]) + # STATE SPRs (dec, tb) + with m.Case(SPR.DEC, SPR.TB): + comb += o.data.eq(state_i) + with m.Case(SPR.TBU): + comb += o.data[0:32].eq(state_i[32:64]) + # slow SPRs TODO comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py index b66c35a0..bdd0608d 100644 --- a/src/soc/fu/spr/pipe_data.py +++ b/src/soc/fu/spr/pipe_data.py @@ -19,6 +19,7 @@ class SPRInputData(IntegerData): regspec = [('INT', 'ra', '0:63'), # RA ('SPR', 'spr1', '0:63'), # SPR (slow) ('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc) + ('STATE', 'state', '0:63'), # SPR (state: DEC, TB) ('XER', 'xer_so', '32'), # XER bit 32: SO ('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32 ('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32 @@ -32,6 +33,7 @@ class SPROutputData(IntegerData): regspec = [('INT', 'o', '0:63'), # RT ('SPR', 'spr1', '0:63'), # SPR (slow) ('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc) + ('STATE', 'state', '0:63'), # SPR (state: DEC, TB) ('XER', 'xer_so', '32'), # XER bit 32: SO ('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32 ('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32 -- 2.30.2