From dc928512d21c7205895f03fc1ce18484512cd94a Mon Sep 17 00:00:00 2001
From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Fri, 14 Sep 2018 17:24:47 +0200
Subject: [PATCH] rs6000: Add another Z to go with Y (PR87224)

This is another case where we ICE because Y does not allow reg+reg, we
need Z for that.


	PR target/87224
	* config/rs6000/rs6000.md (*mov<mode>_hardfloat64): Add Z to the Y
	alternatives.

From-SVN: r264316
---
 gcc/ChangeLog               | 6 ++++++
 gcc/config/rs6000/rs6000.md | 4 ++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 68612fe4223..d3d8287baae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-09-14  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/87224
+	* config/rs6000/rs6000.md (*mov<mode>_hardfloat64): Add Z to the Y
+	alternatives.
+
 2018-09-14  Sam Tebbs  <sam.tebbs@arm.com>
 
 	PR target/85628
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e40dc424073..b0889df395a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7455,13 +7455,13 @@
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
            "=m,           d,          d,          <f64_p9>,   wY,
              <f64_av>,    Z,          <f64_vsx>,  <f64_vsx>,  !r,
-             Y,           r,          !r,         *c*l,       !r,
+             YZ,          r,          !r,         *c*l,       !r,
             *h,           r,          wg,         r,          <f64_dm>")
 
 	(match_operand:FMOVE64 1 "input_operand"
             "d,           m,          d,          wY,         <f64_p9>,
              Z,           <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
-             r,           Y,          r,          r,          h,
+             r,           YZ,         r,          r,          h,
              0,           wg,         r,          <f64_dm>,   r"))]
 
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT
-- 
2.30.2