From dc9dd04c989528e24ee3aace6be107f27b8d9606 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Dec 2021 15:46:11 +0000 Subject: [PATCH] add I-Cache wishbone bus to wb_get when MMU and ROM mode enabled --- src/openpower/test/runner.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index b8378a93..102d3dd5 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -127,10 +127,16 @@ class TestRunnerBase(FHDLTestCase): m = Module() comb = m.d.comb if self.microwatt_mmu: - ldst_ifacetype = 'test_mmu_cache_wb' + # do not wire these up to anything if wb_get is to be used + if self.rom is not None: + ldst_ifacetype = 'mmu_cache_wb' + imem_ifacetype = 'bare_wb' + else: + ldst_ifacetype = 'test_mmu_cache_wb' + imem_ifacetype = 'test_bare_wb' else: ldst_ifacetype = 'test_bare_wb' - imem_ifacetype = 'test_bare_wb' + imem_ifacetype = 'test_bare_wb' pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype, imem_ifacetype=imem_ifacetype, @@ -461,9 +467,12 @@ class TestRunnerBase(FHDLTestCase): # extra emulated process if self.rom is not None: dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache + icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache default_mem = self.rom sim.add_sync_process(wrap(wb_get(dcache.bus, default_mem, "DCACHE"))) + sim.add_sync_process(wrap(wb_get(icache.bus, + default_mem, "ICACHE"))) with sim.write_vcd("issuer_simulator.vcd"): sim.run() -- 2.30.2