From dca710412db18512ef773f55dc998229c4411d57 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 9 Dec 2018 11:27:39 +0000
Subject: [PATCH] mention tiles buffer

---
 3d_gpu/microarchitecture.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index bd20d476e..1f677dc41 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -9,6 +9,8 @@
 * RV64GC compliance for running full GNU/Linux-based OS
 * SimpleV compliance
 * xBitManip (required for VPU and ideal for predication)
+* On-chip tile buffer (memory-mapped SRAM), likely shared
+  between all cores, for the collaborative creation of pixel "tiles".
 * 4-lane 2Rx1W SRAMs for registers numbered 32 and above;
   Multi-R x Multi-W for registers 1-31.
   TODO: consider 2R for registers to be used as predication targets
-- 
2.30.2