From dcafd259a429cbe19fcd93ecf112f887f086ceb9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 5 Jul 2021 22:29:51 +0100 Subject: [PATCH] fix ISACaller FFT-enable detection, fixes sv.fmadds, matrix multiply works --- src/openpower/decoder/isa/test_caller_svp64_matrix.py | 7 +++---- src/openpower/decoder/power_decoder2.py | 6 ++++-- src/openpower/sv/trans/svp64.py | 3 +++ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 926c1b30..7262e1ce 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -33,8 +33,7 @@ class DecoderTestCase(FHDLTestCase): REMAP fmadds FRT, FRA, FRC, FRB """ lst = SVP64Asm(["svremap 2, 2, 3, 0", - "sv.fmadds 0.v, 8.v, 16.v, 0.v" - #"fmadds 0, 0, 0, 4" + "sv.fmadds 0.v, 16.v, 32.v, 0.v" ]) lst = list(lst) @@ -65,8 +64,8 @@ class DecoderTestCase(FHDLTestCase): res = [] # store FPs for i, (x, y) in enumerate(zip(xf, yf)): - fprs[i+8] = fp64toselectable(float(x)) # X matrix - fprs[i+16] = fp64toselectable(float(y)) # Y matrix + fprs[i+16] = fp64toselectable(float(x)) # X matrix + fprs[i+32] = fp64toselectable(float(y)) # Y matrix continue #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 7df9ab52..e2353ff3 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1024,8 +1024,10 @@ class PowerDecodeSubset(Elaboratable): # if bit-reverse mode requested bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE comb += self.use_svp64_ldst_dec.eq(bitrev) - # if SVP64 FFT mode enabled - comb += self.use_svp64_fft.eq(self.is_svp64_mode) + # detect if SVP64 FFT mode enabled (really bad hack) + xo = Signal(2) # 2 bits from Major 59 XO field == 0b00XXX + comb += xo.eq(self.dec.opcode_in[4:6]) + comb += self.use_svp64_fft.eq((major == 59) & (xo == 0b00)) # decoded/selected instruction flags comb += self.do_copy("data_len", self.op_get("ldst_len")) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index beef6a4d..5fa76eeb 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -969,6 +969,9 @@ if __name__ == '__main__': 'sv.ffmadds 6.v, 2.v, 4.v, 6.v', 'svremap 2, 2, 3, 0', ] + lst = [ + 'sv.fmadds 0.v, 8.v, 16.v, 4.v', + ] isa = SVP64Asm(lst, macros=macros) print ("list", list(isa)) csvs = SVP64RM() -- 2.30.2