From dcc2a29f28215104a85371e71787efb854a6aaba Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 18:31:51 +0100 Subject: [PATCH] ehn? moo? CR test_pipe_caller locks up 100% CPU on writing ilang file --- src/soc/fu/cr/test/test_pipe_caller.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 0ee5977d..415ce48e 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -121,9 +121,8 @@ class CRTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = CRBasePipe(pspec) - ports = alu.ports() vl = rtlil.convert(alu, ports=alu.ports()) - with open("logical_pipeline.il", "w") as f: + with open("cr_pipeline.il", "w") as f: f.write(vl) -- 2.30.2