From dcc71bc5aa863b933f4d5dd0fbb9eaac2dfc2c0d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Dec 2021 00:19:54 +0000 Subject: [PATCH] ooo far too late at night to be doing this --- src/soc/experiment/dcache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index ded7e395..cabb5225 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1744,7 +1744,7 @@ class DCache(Elaboratable): # deal with litex not doing wishbone pipeline mode # XXX in wrong way. FIFOs are needed in the SRAM test # so that stb/ack match up. same thing done in icache.py - comb += self.bus.stall.eq(self.bus.cyc & ~bus.ack) + comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack) # Wire up wishbone request latch out of stage 1 comb += self.bus.we.eq(r1.wb.we) -- 2.30.2