From dcdf5df4de22017cfd554d6bdd805b18e3da5242 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Apr 2015 22:50:29 +0200 Subject: [PATCH] adapt LiteEth to new SoC --- misoclib/com/liteeth/example_designs/make.py | 4 +++- misoclib/com/liteeth/example_designs/targets/base.py | 7 ++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py index dcc8bb4c..6f504bb2 100644 --- a/misoclib/com/liteeth/example_designs/make.py +++ b/misoclib/com/liteeth/example_designs/make.py @@ -72,6 +72,8 @@ if __name__ == "__main__": top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() # decode actions action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] @@ -121,7 +123,7 @@ System Clk: {} MHz subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(soc.csr_regions) + csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 3c2a120f..f1d95dd7 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -23,14 +23,15 @@ class BaseSoC(SoC, AutoCSR): mac_address=0x10e2d5000000, ip_address="192.168.0.42"): clk_freq = int((1/(platform.default_clk_period))*1000000000) - self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200) - SoC.__init__(self, platform, clk_freq, self.uart2wb, - with_cpu=False, + SoC.__init__(self, platform, clk_freq, + cpu_type="none", with_csr=True, csr_data_width=32, with_uart=False, with_identifier=True, with_timer=False ) + self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # wishbone SRAM (to test Wishbone over UART and Etherbone) -- 2.30.2