From dcebf3aa49cd10d61c898df6a9711c8d3247492a Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 23 Jun 2022 14:55:24 +0100 Subject: [PATCH] --- openpower/sv/sprs.mdwn | 72 +++++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 33 deletions(-) diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn index aae560cf4..1913c1b2c 100644 --- a/openpower/sv/sprs.mdwn +++ b/openpower/sv/sprs.mdwn @@ -9,13 +9,11 @@ Note OpenPOWER v3.1 p12: There are five SPRs, available in any privilege level: -* MVL (the Maximum Vector Length) -* VL (which has different characteristics from standard SPRs) -* SUBVL (effectively a kind of Packed SIMD of size 2, 3 or 4) * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information) * SVSRR0 which is used for exceptions and traps to store SVSTATE. - -MVL, VL and SUBVL are only provided for convenience: normally [[sv/setvl]] would be used to obtain a copy of VL, for example. +* SVLR, a mirror of LR, used by Vectorised Branch +* SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops +* SVREMAP for applying specific shapes to specific registers For Privilege Levels (trap handling) there are the following SPRs, where x may be u, s or h for User, Supervisor or Hypervisor @@ -28,39 +26,14 @@ The u/s SPRs are treated and handled exactly like their (x)epc equivalents. On entry to or exit from a privilege level, the contents of its (x)eSTATE are swapped with SVSTATE. -# MAXVECTORLENGTH (MVL) - -MAXVECTORLENGTH is the same concept as MVL in RVV, except that it -is variable length and may be dynamically set. MVL is -however limited to the regfile bitwidth, 64. - -# Vector Length (VL) - -VSETVL is slightly different from RVV. Similar to RVV, VL is set to be within -the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN) - - VL = rd = MIN(vlen, MVL) - -where 1 <= MVL <= XLEN - -# SUBVL - Sub Vector Length - -This is a "group by quantity" that effectively asks each iteration -of the hardware loop to load SUBVL elements of width elwidth at a -time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1 -operation issued, SUBVL operations are issued. - -The main effect of SUBVL is that predication bits are applied per -**group**, rather than by individual element. Legal values are 1 to 4. -Illegal values raise an exception. - # SVSTATE This is a standard SPR that contains sufficient information for a full context save/restore (see SVSRR0). It contains (and permits setting of): -* MVL -* VL +* MVL (the Maximum Vector Length) - declares (statically) how + much of a regfile is to be reserved for Vector elements +* VL - Vector Length * dststep - the destination element offset of the current parallel instruction being executed * srcstep - for twin-predication, the source element offset as well. @@ -83,6 +56,32 @@ full context save/restore (see SVSRR0). It contains (and permits setting of): indicate the SVSHAPE (0-3) that the corresponding register (RA etc) should use. +**MAXVECTORLENGTH (MVL)** + +MAXVECTORLENGTH is the same concept as MVL in RVV, except that it +is variable length and may be dynamically set. MVL is +however limited to the regfile bitwidth, 64. + +**Vector Length (VL)** + +VSETVL is slightly different from RVV. Similar to RVV, VL is set to be within +the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN) + + VL = rd = MIN(vlen, MVL) + +where 1 <= MVL <= XLEN + +**SUBVL - Sub Vector Length** + +This is a "group by quantity" that effectively asks each iteration +of the hardware loop to load SUBVL elements of width elwidth at a +time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1 +operation issued, SUBVL operations are issued. + +The main effect of SUBVL is that predication bits are applied per +**group**, rather than by individual element. Legal values are 1 to 4. +Illegal values raise an exception. + For hphint, the number chosen must be consistently executed **every time**. Hardware is not permitted to execute five computations for one instruction then three on the next. @@ -148,3 +147,10 @@ time that SRR0 is saved/restored in PC and SRR1 in MSR. The SPR name given for the purposes of saving/restoring SVSTATE is SVSRR0. + +# SVLR + +SV Link Register, exactly analogous to LR (Link Register) may +be used for temporary storage of SVSTATE, and, in particular, +Vectorised Branch-Conditional instructions may interchange +SVLR and SVSTATE whenever LR and NIA are. -- 2.30.2