From dcfe04fdaa5603e1b12308ae9893644b40fa8c71 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Apr 2021 21:08:14 +0100 Subject: [PATCH] upload 32-bit wishbone data not 64-bit test data --- ls180/post_pnr/cocotb/test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py index 718faf5..a96846c 100644 --- a/ls180/post_pnr/cocotb/test.py +++ b/ls180/post_pnr/cocotb/test.py @@ -172,12 +172,12 @@ def wishbone_basic(dut): yield master.load_ir(cmd_MEMREADWRITE) dut._log.info("Writing memory") - data_in.binstr = "01010101" * 8 + data_in.binstr = "01010101" * 4 dut._log.info(" input: {}".format(data_in.binstr)) yield master.shift_data(data_in) dut._log.info(" output: {}".format(master.result.binstr)) - data_in.binstr = "10101010" * 8 + data_in.binstr = "10101010" * 4 dut._log.info(" input: {}".format(data_in.binstr)) yield master.shift_data(data_in) dut._log.info(" output: {}".format(master.result.binstr)) -- 2.30.2