From dd1bdce4183a38fe030154fdf7b86a9b397e6ae2 Mon Sep 17 00:00:00 2001 From: Venkataramanan Kumar Date: Tue, 26 May 2015 15:32:02 +0000 Subject: [PATCH] re PR target/66049 (Few AArch64 extend and add with shift tests generates sub optimal code with trunk gcc 6.0.) 2015-05-26 Venkataramanan Kumar PR target/66049 * config/aarch64/aarch64.md (*adds_shift_imm_): New pattern. (*subs_shift_imm_): Likewise. (*adds__shift_): Likewise. (*subs__shift_): Likewise. (*add_uxt_shift2): Likewise. (*add_uxtsi_shift2_uxtw): Likewise. (*sub_uxt_shift2): Likewise. (*sub_uxtsi_shift2_uxtw): Likewise. From-SVN: r223703 --- gcc/ChangeLog | 13 ++++ gcc/config/aarch64/aarch64.md | 132 ++++++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 23e92d8e1cb..cc7c30a8897 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2015-05-26 Venkataramanan Kumar + + PR target/66049 + * config/aarch64/aarch64.md + (*adds_shift_imm_): New pattern. + (*subs_shift_imm_): Likewise. + (*adds__shift_): Likewise. + (*subs__shift_): Likewise. + (*add_uxt_shift2): Likewise. + (*add_uxtsi_shift2_uxtw): Likewise. + (*sub_uxt_shift2): Likewise. + (*sub_uxtsi_shift2_uxtw): Likewise. + 2015-05-26 David Edelsohn * config/rs6000/constraints.md (Y, U): Use match_test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4817fae5d32..258443d6fd3 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1539,6 +1539,38 @@ [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) +(define_insn "*adds_shift_imm_" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (plus:GPI (ASHIFT:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_" "n")) + (match_operand:GPI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2)) + (match_dup 3)))] + "" + "adds\\t%0, %3, %1, %2" + [(set_attr "type" "alus_shift_imm")] +) + +(define_insn "*subs_shift_imm_" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (minus:GPI (match_operand:GPI 1 "register_operand" "r") + (ASHIFT:GPI + (match_operand:GPI 2 "register_operand" "r") + (match_operand:QI 3 "aarch64_shift_imm_" "n"))) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (minus:GPI (match_dup 1) + (ASHIFT:GPI (match_dup 2) (match_dup 3))))] + "" + "subs\\t%0, %1, %2, %3" + [(set_attr "type" "alus_shift_imm")] +) + (define_insn "*adds_mul_imm_" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -1599,6 +1631,42 @@ [(set_attr "type" "alus_ext")] ) +(define_insn "*adds__shift_" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (plus:GPI (ashift:GPI + (ANY_EXTEND:GPI + (match_operand:ALLX 1 "register_operand" "r")) + (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand:GPI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (ashift:GPI (ANY_EXTEND:GPI (match_dup 1)) + (match_dup 2)) + (match_dup 3)))] + "" + "adds\\t%0, %3, %1, xt %2" + [(set_attr "type" "alus_ext")] +) + +(define_insn "*subs__shift_" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (minus:GPI (match_operand:GPI 1 "register_operand" "r") + (ashift:GPI + (ANY_EXTEND:GPI + (match_operand:ALLX 2 "register_operand" "r")) + (match_operand 3 "aarch64_imm3" "Ui3"))) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_dup 1) + (ashift:GPI (ANY_EXTEND:GPI (match_dup 2)) + (match_dup 3))))] + "" + "subs\\t%0, %1, %2, xt %3" + [(set_attr "type" "alus_ext")] +) + (define_insn "*adds__multp2" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -1894,6 +1962,38 @@ [(set_attr "type" "adc_reg")] ) +(define_insn "*add_uxt_shift2" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (plus:GPI (and:GPI + (ashift:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 3 "const_int_operand" "n")) + (match_operand:GPI 4 "register_operand" "r")))] + "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0" + "* + operands[3] = GEN_INT (aarch64_uxt_size (INTVAL(operands[2]), + INTVAL (operands[3]))); + return \"add\t%0, %4, %1, uxt%e3 %2\";" + [(set_attr "type" "alu_ext")] +) + +;; zero_extend version of above +(define_insn "*add_uxtsi_shift2_uxtw" + [(set (match_operand:DI 0 "register_operand" "=rk") + (zero_extend:DI + (plus:SI (and:SI + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 3 "const_int_operand" "n")) + (match_operand:SI 4 "register_operand" "r"))))] + "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0" + "* + operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]), + INTVAL (operands[3]))); + return \"add\t%w0, %w4, %w1, uxt%e3 %2\";" + [(set_attr "type" "alu_ext")] +) + (define_insn "*add_uxt_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (plus:GPI (and:GPI @@ -2150,6 +2250,38 @@ [(set_attr "type" "adc_reg")] ) +(define_insn "*sub_uxt_shift2" + [(set (match_operand:GPI 0 "register_operand" "=rk") + (minus:GPI (match_operand:GPI 4 "register_operand" "rk") + (and:GPI + (ashift:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 3 "const_int_operand" "n"))))] + "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0" + "* + operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]), + INTVAL (operands[3]))); + return \"sub\t%0, %4, %1, uxt%e3 %2\";" + [(set_attr "type" "alu_ext")] +) + +;; zero_extend version of above +(define_insn "*sub_uxtsi_shift2_uxtw" + [(set (match_operand:DI 0 "register_operand" "=rk") + (zero_extend:DI + (minus:SI (match_operand:SI 4 "register_operand" "rk") + (and:SI + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "aarch64_imm3" "Ui3")) + (match_operand 3 "const_int_operand" "n")))))] + "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0" + "* + operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]), + INTVAL (operands[3]))); + return \"sub\t%w0, %w4, %w1, uxt%e3 %2\";" + [(set_attr "type" "alu_ext")] +) + (define_insn "*sub_uxt_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "rk") -- 2.30.2