From dd2614285995f1c975c5f9a815eec6cd94316e5d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 May 2021 15:18:51 +0100 Subject: [PATCH] more rename of exception_o to exc_o, add convenience function in TestCore to get at all exceptions --- src/soc/experiment/pi2ls.py | 2 +- src/soc/experiment/pimem.py | 6 +++--- src/soc/fu/compunits/compunits.py | 20 +++++++++++++++----- src/soc/fu/mmu/fsm.py | 2 +- 4 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index abba37e1..f07ba33c 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -14,7 +14,7 @@ addr.ok/1 probably x_valid_i & ~x_stall_i addr_ok_o/1 no equivalent. *might* work using x_stall_i - exception_o/2(?) m_load_err_o and m_store_err_o + exc_o/6(?) m_load_err_o and m_store_err_o ld.data/64 m_ld_data_o ld.ok/1 probably implicit, when x_busy drops low diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 1a66b914..e9923ca6 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -107,7 +107,7 @@ class PortInterface(RecordObject): self.addr = Data(addrwid, "addr_i") # addr/addr-ok # addr is valid (TLB, L1 etc.) self.addr_ok_o = Signal(reset_less=True) - self.exception_o = LDSTException("exc") + self.exc_o = LDSTException("exc") # LD/ST self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf @@ -139,7 +139,7 @@ class PortInterface(RecordObject): inport.ld.eq(self.ld), inport.busy_o.eq(self.busy_o), inport.addr_ok_o.eq(self.addr_ok_o), - inport.exception_o.eq(self.exception_o), + inport.exc_o.eq(self.exc_o), inport.mmu_done.eq(self.mmu_done), inport.ldst_error.eq(self.ldst_error), inport.cache_paradox.eq(self.cache_paradox) @@ -291,7 +291,7 @@ class PortInterfaceBase(Elaboratable): comb += st_done.r.eq(1) # store done reset # monitor for an exception or the completion of LD. - with m.If(self.pi.exception_o.happened): + with m.If(self.pi.exc_o.happened): comb += busy_l.r.eq(1) # however ST needs one cycle before busy is reset diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index e628c082..930fd147 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -266,24 +266,34 @@ class AllFunctionUnits(Elaboratable): else: alus['div'] = DivPipeFunctionUnit + # create dictionary of Function Units self.fus = {} for name, qty in units.items(): kls = alus[name] for i in range(qty): self.fus["%s%d" % (name, i)] = kls(i) + + # debug print for MMU ALU if microwatt_mmu: - print("cut here ==============================") alu = self.fus["mmu0"].alu - print("alu", alu) - #pi = alu.pi - #print("pi", pi) - #pilist = [pi] + print("MMU alu", alu) + + # if any PortInterfaces, we want LDST Units. if pilist is None: return print ("pilist", pilist) for i, pi in enumerate(pilist): self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i) + # extract exceptions from any FunctionUnits for easy access + self.excs = {} + for name, alu in self.fus.items(): + if hasattr(alu, "exc_o"): + self.excs[name] = alu.exc_o + + def get_exc(self, name): + return self.excs.get(name, default=None) + def get_fu(self, name): return self.fus.get(name) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index ce8185b4..af92d68d 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -150,7 +150,7 @@ class LoadStore1(PortInterfaceBase): # v.state := MMU_LOOKUP; # v.stage1_en := '0'; - exc = self.pi.exception_o + exc = self.pi.exc_o #happened, alignment, instr_fault, invalid, comb += exc.happened.eq(d_out.error | l_out.err) -- 2.30.2