From dd47d2caf101216ca1675f1fcd8d490e65684f16 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 12:56:42 +0100 Subject: [PATCH] add SPR pipeline --- src/soc/fu/spr/pipeline.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 src/soc/fu/spr/pipeline.py diff --git a/src/soc/fu/spr/pipeline.py b/src/soc/fu/spr/pipeline.py new file mode 100644 index 00000000..fc3c7c29 --- /dev/null +++ b/src/soc/fu/spr/pipeline.py @@ -0,0 +1,22 @@ +from nmutil.singlepipe import ControlBase +from nmutil.pipemodbase import PipeModBaseChain +from soc.fu.trap.main_stage import SPRMainStage + +class SPRStages(PipeModBaseChain): + def get_chain(self): + main = SPRMainStage(self.pspec) + return [main] + + +class SPRBasePipe(ControlBase): + def __init__(self, pspec): + ControlBase.__init__(self) + self.pspec = pspec + self.pipe1 = SPRStages(pspec) + self._eqs = self.connect([self.pipe1]) + + def elaborate(self, platform): + m = ControlBase.elaborate(self, platform) + m.submodules.pipe = self.pipe1 + m.d.comb += self._eqs + return m -- 2.30.2