From dd5af1d61761e9bf466cd64360e6321cde0a2c5f Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Tue, 6 Dec 2016 22:15:31 +0000 Subject: [PATCH] re PR target/78658 (powerpc64le: ICE with -mcpu=power9 -Og) [gcc] 2016-12-06 Michael Meissner PR target/78658 * config/rs6000/rs6000.md (zero_extendqi2): Use ^ instead of ?* constraints for the ISA 3.0 patterns, so the register allocator is more likely to allocate QImode/HImode to vector registers for conversion to floating point unless a reload is needed. (zero_extendhi2): Likewise. (float2_internal): Properly deal with the first alternative which is converting QImode/HImode to floating point and the QImode/HImode value is in a vector register, and does not allocate the second pseudo register. Remove zero extending into traditional floating point registers, since the instruction used only works on traditional altivec registers. (floatuns2_internal): Likewise. [gcc/testsuite] 2016-12-06 Michael Meissner PR target/78658 * gcc.target/powerpc/pr78658.c: New test. From-SVN: r243320 --- gcc/ChangeLog | 16 ++++++++++++++++ gcc/config/rs6000/rs6000.md | 21 ++++++++++++++------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/pr78658.c | 14 ++++++++++++++ 4 files changed, 49 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78658.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 85916c15575..463dc1a37d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2016-12-06 Michael Meissner + + PR target/78658 + * config/rs6000/rs6000.md (zero_extendqi2): Use ^ instead of + ?* constraints for the ISA 3.0 patterns, so the register allocator + is more likely to allocate QImode/HImode to vector registers for + conversion to floating point unless a reload is needed. + (zero_extendhi2): Likewise. + (float2_internal): Properly deal with the + first alternative which is converting QImode/HImode to floating + point and the QImode/HImode value is in a vector register, and + does not allocate the second pseudo register. Remove zero + extending into traditional floating point registers, since the + instruction used only works on traditional altivec registers. + (floatuns2_internal): Likewise. + 2016-12-06 David Malcolm * config/i386/i386.c: Include print-rtl.h. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5a453a08e6b..4726d73d573 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -738,8 +738,8 @@ ;; complex forms. Basic data transfer is done later. (define_insn "zero_extendqi2" - [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,?*wJwK,?*wK") - (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,*wK")))] + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wJwK,^wK") + (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,wK")))] "" "@ lbz%U1%X1 %0,%1 @@ -791,7 +791,7 @@ (define_insn "zero_extendhi2" - [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wJwK,?*wK") + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wJwK,^wK") (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))] "" "@ @@ -5413,11 +5413,13 @@ if (!MEM_P (input)) { + rtx tmp = operands[3]; if (altivec_register_operand (input, mode)) emit_insn (gen_extenddi2 (di, input)); + else if (GET_CODE (tmp) == SCRATCH) + emit_insn (gen_extenddi2 (di, input)); else { - rtx tmp = operands[3]; emit_insn (gen_extenddi2 (tmp, input)); emit_move_insn (di, tmp); } @@ -5449,7 +5451,7 @@ (define_insn_and_split "*floatuns2_internal" [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=,,") (unsigned_float:FP_ISA3 - (match_operand:QHI 1 "reg_or_indexed_operand" "wJwK,r,Z"))) + (match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z"))) (clobber (match_scratch:DI 2 "=wK,wi,wJwK")) (clobber (match_scratch:DI 3 "=X,r,X"))] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64 @@ -5467,8 +5469,13 @@ else { rtx tmp = operands[3]; - emit_insn (gen_zero_extenddi2 (tmp, input)); - emit_move_insn (di, tmp); + if (GET_CODE (tmp) == SCRATCH) + emit_insn (gen_extenddi2 (di, input)); + else + { + emit_insn (gen_zero_extenddi2 (tmp, input)); + emit_move_insn (di, tmp); + } } emit_insn (gen_floatdi2 (result, di)); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 95167b3d8de..5adcdd2c40a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-12-06 Michael Meissner + + PR target/78658 + * gcc.target/powerpc/pr78658.c: New test. + 2016-12-06 Vladimir Makarov target/77761 diff --git a/gcc/testsuite/gcc.target/powerpc/pr78658.c b/gcc/testsuite/gcc.target/powerpc/pr78658.c new file mode 100644 index 00000000000..fcea632c31c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78658.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* This caused an unrecognizable insn message on development versions of GCC 7. */ + +float a; +char b; + +void c(void) +{ + a = b = a; +} -- 2.30.2