From dd7135d55d5bfbbcd278a2ca33b6b8cc04776080 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Sat, 18 Aug 2018 16:42:04 -0700 Subject: [PATCH] intel/compiler: Use the flrp lowering pass for all stages on Gen4 and Gen5 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Previously lower_flrp32 was only set for vertex shaders. Fragment shaders performed a(1-c)+bc lowering during code generation. The shaders with loops hurt are SIMD8 and SIMD16 shaders for a text-identical fragment shader. v2: Rebase on 26391cceaa1 ("intel/compiler: Lower ffma on Gen4 and Gen5"). v3: Rebase on a004e95dd73 ("radeonsi/nir: create si_nir_opts() helper") Iron Lake total instructions in shared programs: 8211385 -> 8185974 (-0.31%) instructions in affected programs: 2503898 -> 2478487 (-1.01%) helped: 9936 HURT: 921 helped stats (abs) min: 1 max: 155 x̄: 2.86 x̃: 2 helped stats (rel) min: 0.10% max: 35.48% x̄: 1.67% x̃: 1.11% HURT stats (abs) min: 1 max: 12 x̄: 3.24 x̃: 2 HURT stats (rel) min: 0.21% max: 13.64% x̄: 1.86% x̃: 0.89% 95% mean confidence interval for instructions value: -2.43 -2.25 95% mean confidence interval for instructions %-change: -1.41% -1.33% Instructions are helped. total cycles in shared programs: 188523186 -> 188401198 (-0.06%) cycles in affected programs: 71541604 -> 71419616 (-0.17%) helped: 11649 HURT: 1871 helped stats (abs) min: 2 max: 930 x̄: 12.62 x̃: 6 helped stats (rel) min: <.01% max: 44.61% x̄: 0.68% x̃: 0.25% HURT stats (abs) min: 2 max: 138 x̄: 13.38 x̃: 8 HURT stats (rel) min: <.01% max: 10.99% x̄: 0.49% x̃: 0.17% 95% mean confidence interval for cycles value: -9.42 -8.63 95% mean confidence interval for cycles %-change: -0.54% -0.50% Cycles are helped. total loops in shared programs: 852 -> 856 (0.47%) loops in affected programs: 0 -> 4 helped: 0 HURT: 4 HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.00% max: 0.00% x̄: 0.00% x̃: 0.00% 95% mean confidence interval for loops value: 1.00 1.00 95% mean confidence interval for loops %-change: 0.00% 0.00% Loops are HURT. LOST: 3 GAINED: 12 GM45 total instructions in shared programs: 5046407 -> 5033694 (-0.25%) instructions in affected programs: 1303584 -> 1290871 (-0.98%) helped: 5010 HURT: 464 helped stats (abs) min: 1 max: 155 x̄: 2.85 x̃: 2 helped stats (rel) min: 0.10% max: 34.38% x̄: 1.63% x̃: 1.08% HURT stats (abs) min: 1 max: 75 x̄: 3.39 x̃: 2 HURT stats (rel) min: 0.20% max: 13.04% x̄: 1.84% x̃: 0.87% 95% mean confidence interval for instructions value: -2.45 -2.20 95% mean confidence interval for instructions %-change: -1.40% -1.28% Instructions are helped. total cycles in shared programs: 128889476 -> 128812366 (-0.06%) cycles in affected programs: 44845402 -> 44768292 (-0.17%) helped: 6079 HURT: 940 helped stats (abs) min: 2 max: 930 x̄: 15.16 x̃: 8 helped stats (rel) min: <.01% max: 41.03% x̄: 0.71% x̃: 0.25% HURT stats (abs) min: 2 max: 138 x̄: 16.01 x̃: 8 HURT stats (rel) min: <.01% max: 10.99% x̄: 0.50% x̃: 0.17% 95% mean confidence interval for cycles value: -11.63 -10.34 95% mean confidence interval for cycles %-change: -0.58% -0.52% Cycles are helped. total loops in shared programs: 633 -> 635 (0.32%) loops in affected programs: 0 -> 2 helped: 0 HURT: 2 total spills in shared programs: 60 -> 69 (15.00%) spills in affected programs: 54 -> 63 (16.67%) helped: 0 HURT: 1 total fills in shared programs: 92 -> 105 (14.13%) fills in affected programs: 80 -> 93 (16.25%) helped: 0 HURT: 1 LOST: 15 GAINED: 15 Reviewed-by: Jason Ekstrand [v2] Reviewed-by: Matt Turner [v2] --- src/gallium/drivers/radeonsi/si_shader_nir.c | 12 ++++++------ src/intel/compiler/brw_compiler.c | 14 ++++---------- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index afc8d5f3b78..febd0e49a2c 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -816,9 +816,9 @@ si_nir_opts(struct nir_shader *nir) { bool progress; unsigned lower_flrp = - (sel->nir->options->lower_flrp16 ? 16 : 0) | - (sel->nir->options->lower_flrp32 ? 32 : 0) | - (sel->nir->options->lower_flrp64 ? 64 : 0); + (nir->options->lower_flrp16 ? 16 : 0) | + (nir->options->lower_flrp32 ? 32 : 0) | + (nir->options->lower_flrp64 ? 64 : 0); do { progress = false; @@ -852,12 +852,12 @@ si_nir_opts(struct nir_shader *nir) if (lower_flrp != 0) { bool lower_flrp_progress; - NIR_PASS(lower_flrp_progress, sel->nir, nir_lower_flrp, + NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */, - sel->nir->options->lower_ffma); + nir->options->lower_ffma); if (lower_flrp_progress) { - NIR_PASS(progress, sel->nir, + NIR_PASS(progress, nir, nir_opt_constant_folding); progress = true; } diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index b119a758768..626ff4bb16a 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -170,21 +170,15 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) rzalloc(compiler, struct nir_shader_compiler_options); if (is_scalar) { *nir_options = scalar_nir_options; - - if (devinfo->gen >= 11) { - nir_options->lower_flrp32 = true; - } } else { *nir_options = vector_nir_options; - - if (devinfo->gen < 6) { - /* Prior to Gen6, there are no three source operations. */ - nir_options->lower_flrp32 = true; - } } - /* Prior to Gen6, there are no three source operations. */ + /* Prior to Gen6, there are no three source operations, and Gen11 loses + * LRP. + */ nir_options->lower_ffma = devinfo->gen < 6; + nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11; nir_options->lower_int64_options = int64_options; nir_options->lower_doubles_options = fp64_options; -- 2.30.2