From dd77684f05433afcba15743ba1e2445804f9ac9f Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 2 May 2016 18:46:10 +0200 Subject: [PATCH] re PR rtl-optimization/70467 (Useless "and [esp],-1" emitted on AND with uint64_t variable) PR rtl-optimization/70467 * cse.c (cse_insn): Handle no-op MEM moves after folding. * gcc.target/i386/pr70467-1.c: New test. From-SVN: r235765 --- gcc/ChangeLog | 3 ++ gcc/cse.c | 28 +++++++++++- gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/gcc.target/i386/pr70467-1.c | 55 +++++++++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr70467-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5bf2ffa7c35..a5339da2527 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2016-05-02 Jakub Jelinek + PR rtl-optimization/70467 + * cse.c (cse_insn): Handle no-op MEM moves after folding. + PR rtl-optimization/70467 * ipa-pure-const.c (check_call): Handle internal calls even in ipa mode like in local mode. diff --git a/gcc/cse.c b/gcc/cse.c index 2665d9a2733..7456e84c329 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -4575,6 +4575,7 @@ cse_insn (rtx_insn *insn) for (i = 0; i < n_sets; i++) { bool repeat = false; + bool mem_noop_insn = false; rtx src, dest; rtx src_folded; struct table_elt *elt = 0, *p; @@ -5166,7 +5167,7 @@ cse_insn (rtx_insn *insn) } /* Avoid creation of overlapping memory moves. */ - if (MEM_P (trial) && MEM_P (SET_DEST (sets[i].rtl))) + if (MEM_P (trial) && MEM_P (dest) && !rtx_equal_p (trial, dest)) { rtx src, dest; @@ -5277,6 +5278,21 @@ cse_insn (rtx_insn *insn) break; } + /* Similarly, lots of targets don't allow no-op + (set (mem x) (mem x)) moves. */ + else if (n_sets == 1 + && MEM_P (trial) + && MEM_P (dest) + && rtx_equal_p (trial, dest) + && !side_effects_p (dest) + && (cfun->can_delete_dead_exceptions + || insn_nothrow_p (insn))) + { + SET_SRC (sets[i].rtl) = trial; + mem_noop_insn = true; + break; + } + /* Reject certain invalid forms of CONST that we create. */ else if (CONSTANT_P (trial) && GET_CODE (trial) == CONST @@ -5495,6 +5511,16 @@ cse_insn (rtx_insn *insn) sets[i].rtl = 0; } + /* Similarly for no-op MEM moves. */ + else if (mem_noop_insn) + { + if (cfun->can_throw_non_call_exceptions && can_throw_internal (insn)) + cse_cfg_altered = true; + delete_insn_and_edges (insn); + /* No more processing for this set. */ + sets[i].rtl = 0; + } + /* If this SET is now setting PC to a label, we know it used to be a conditional or computed branch. */ else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7d7dae4dcf9..328a9a5f056 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-05-02 Jakub Jelinek + + PR rtl-optimization/70467 + * gcc.target/i386/pr70467-1.c: New test. + 2016-05-02 Bernd Edlinger * gcc.dg/spec-options.c: Run the test on all targets. diff --git a/gcc/testsuite/gcc.target/i386/pr70467-1.c b/gcc/testsuite/gcc.target/i386/pr70467-1.c new file mode 100644 index 00000000000..4e112c88d07 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70467-1.c @@ -0,0 +1,55 @@ +/* PR rtl-optimization/70467 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-sse" } */ + +void foo (unsigned long long *); + +void +bar (void) +{ + unsigned long long a; + foo (&a); + a &= 0x7fffffffffffffffULL; + foo (&a); + a &= 0xffffffff7fffffffULL; + foo (&a); + a &= 0x7fffffff00000000ULL; + foo (&a); + a &= 0x000000007fffffffULL; + foo (&a); + a &= 0x00000000ffffffffULL; + foo (&a); + a &= 0xffffffff00000000ULL; + foo (&a); + a |= 0x7fffffffffffffffULL; + foo (&a); + a |= 0xffffffff7fffffffULL; + foo (&a); + a |= 0x7fffffff00000000ULL; + foo (&a); + a |= 0x000000007fffffffULL; + foo (&a); + a |= 0x00000000ffffffffULL; + foo (&a); + a |= 0xffffffff00000000ULL; + foo (&a); + a ^= 0x7fffffffffffffffULL; + foo (&a); + a ^= 0xffffffff7fffffffULL; + foo (&a); + a ^= 0x7fffffff00000000ULL; + foo (&a); + a ^= 0x000000007fffffffULL; + foo (&a); + a ^= 0x00000000ffffffffULL; + foo (&a); + a ^= 0xffffffff00000000ULL; + foo (&a); +} + +/* { dg-final { scan-assembler-not "andl\[ \t\]*.-1," { target ia32 } } } */ +/* { dg-final { scan-assembler-not "andl\[ \t\]*.0," { target ia32 } } } */ +/* { dg-final { scan-assembler-not "orl\[ \t\]*.-1," { target ia32 } } } */ +/* { dg-final { scan-assembler-not "orl\[ \t\]*.0," { target ia32 } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]*.-1," { target ia32 } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]*.0," { target ia32 } } } */ -- 2.30.2