From dd7b9a5d55594de7ba028b2c0bfffa94a611a127 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 21 Mar 2021 21:52:47 -0300 Subject: [PATCH] Add traces for the new FSM and integer predicate decoding --- src/soc/simple/test/test_runner.py | 36 +++++++++++++++++++----------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 48c1b6d4..75c95742 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -330,25 +330,35 @@ class TestRunner(FHDLTestCase): traces = [ 'clk', - {'comment': 'state machines'}, - 'fetch_pc_valid_i', 'fetch_pc_ready_o', - 'fetch_fsm_state', - 'fetch_insn_valid_o', 'fetch_insn_ready_i', - 'issue_fsm_state', - 'exec_insn_valid_i', 'exec_insn_ready_o', - 'exec_fsm_state', - 'exec_pc_valid_o', 'exec_pc_ready_i', - 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed', - 'is_last', 'dec2.no_out_vec', + ('state machines', 'closed', [ + 'fetch_pc_valid_i', 'fetch_pc_ready_o', + 'fetch_fsm_state', + 'fetch_insn_valid_o', 'fetch_insn_ready_i', + 'pred_insn_valid_i', 'pred_insn_ready_o', + 'fetch_predicate_state', + 'pred_mask_valid_o', 'pred_mask_ready_i', + 'issue_fsm_state', + 'exec_insn_valid_i', 'exec_insn_ready_o', + 'exec_fsm_state', + 'exec_pc_valid_o', 'exec_pc_ready_i', + 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed', + 'is_last', 'dec2.no_out_vec']), {'comment': 'fetch and decode'}, (None, 'dec', [ 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'cur_pc[63:0]', 'core_core_cia[63:0]']), 'raw_insn_i[31:0]', 'raw_opcode_in[31:0]', 'insn_type', - {'comment': 'svp64 decoding'}, - 'svp64_rm[23:0]', - ('dec2.extra[8:0]', 'bin'), + ('svp64 decoding', 'closed', [ + 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'), + 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode', + 'dec2.sv_rm_dec.ptype_in', + 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]', + 'dstmask[63:0]', 'srcmask[63:0]', + 'dregread[4:0]', 'dinvert', + 'sregread[4:0]', 'sinvert', + 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]', + 'core.int.pred__ren']), ('register augmentation', 'dec', 'closed', [ {'comment': 'v3.0b registers'}, 'dec2.dec_o.RT[4:0]', -- 2.30.2