From dd84c610a68a556eb532cee133df68c4354dbf32 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 10 Oct 2021 13:26:49 +0100 Subject: [PATCH] replace PartitionedSignal with SimdSignal --- pinmux | 2 +- src/soc/fu/alu/main_stage.py | 2 +- src/soc/fu/alu/output_stage.py | 2 +- src/soc/fu/common_output_stage.py | 2 +- src/soc/fu/div/core_stages.py | 2 +- src/soc/fu/div/output_stage.py | 2 +- src/soc/fu/div/setup_stage.py | 2 +- src/soc/fu/logical/main_stage.py | 2 +- src/soc/fu/logical/output_stage.py | 2 +- src/soc/fu/mul/main_stage.py | 2 +- src/soc/fu/mul/post_stage.py | 2 +- src/soc/fu/mul/pre_stage.py | 2 +- src/soc/fu/shift_rot/main_stage.py | 2 +- src/soc/litex/florent | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/pinmux b/pinmux index 096caad8..d96f737c 160000 --- a/pinmux +++ b/pinmux @@ -1 +1 @@ -Subproject commit 096caad8418250693c93ccf90047750704adcaa7 +Subproject commit d96f737c0a53dde983060522816bbef016b449ce diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index 4d5fe231..f4ad4918 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -13,7 +13,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts, extz from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp from openpower.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index 49444e97..395b268b 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Cat, Repl) from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from soc.fu.common_output_stage import CommonOutputStage -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index dc17410a..45106984 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -2,7 +2,7 @@ # and updating the condition register from nmigen import (Module, Signal, Cat, Const) from nmutil.pipemodbase import PipeModBase -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py index 9f63a631..e271876b 100644 --- a/src/soc/fu/div/core_stages.py +++ b/src/soc/fu/div/core_stages.py @@ -3,7 +3,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp from openpower.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index 903770dd..31218c66 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -8,7 +8,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array, signed) from nmutil.pipemodbase import PipeModBase from soc.fu.logical.pipe_data import LogicalInputData from soc.fu.div.pipe_data import DivMulOutputData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp from openpower.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py index 937bcbb0..0625159e 100644 --- a/src/soc/fu/div/setup_stage.py +++ b/src/soc/fu/div/setup_stage.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DivInputData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp from openpower.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index e56f3445..25366403 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -13,7 +13,7 @@ from soc.fu.logical.pipe_data import LogicalInputData from soc.fu.logical.bpermd import Bpermd from soc.fu.logical.popcount import Popcount from soc.fu.logical.pipe_data import LogicalOutputData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp from openpower.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/logical/output_stage.py b/src/soc/fu/logical/output_stage.py index 73b48d1e..81a1c524 100644 --- a/src/soc/fu/logical/output_stage.py +++ b/src/soc/fu/logical/output_stage.py @@ -6,7 +6,7 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.common_output_stage import CommonOutputStage from soc.fu.logical.pipe_data import (LogicalInputData, LogicalOutputData, LogicalOutputDataFinal) -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp diff --git a/src/soc/fu/mul/main_stage.py b/src/soc/fu/mul/main_stage.py index 68bcf47d..e2a2727f 100644 --- a/src/soc/fu/mul/main_stage.py +++ b/src/soc/fu/mul/main_stage.py @@ -3,7 +3,7 @@ from nmigen import Module from nmutil.pipemodbase import PipeModBase from soc.fu.mul.pipe_data import MulIntermediateData, MulOutputData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal class MulMainStage2(PipeModBase): diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py index 0b45c791..d7e8df41 100644 --- a/src/soc/fu/mul/post_stage.py +++ b/src/soc/fu/mul/post_stage.py @@ -10,7 +10,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, signed) from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DivMulOutputData from soc.fu.mul.pipe_data import MulOutputData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp diff --git a/src/soc/fu/mul/pre_stage.py b/src/soc/fu/mul/pre_stage.py index f22964dd..c5e696ae 100644 --- a/src/soc/fu/mul/pre_stage.py +++ b/src/soc/fu/mul/pre_stage.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Mux) from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DivInputData from soc.fu.mul.pipe_data import MulIntermediateData -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from nmutil.util import eq32 class MulMainStage1(PipeModBase): diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index 0be12d1b..76550854 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -10,7 +10,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData, ShiftRotInputData) -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from openpower.decoder.power_enums import MicrOp from soc.fu.shift_rot.rotator import Rotator diff --git a/src/soc/litex/florent b/src/soc/litex/florent index b55917aa..42f73576 160000 --- a/src/soc/litex/florent +++ b/src/soc/litex/florent @@ -1 +1 @@ -Subproject commit b55917aafa6bbc9f16e1d97dc095e929c31aa81a +Subproject commit 42f7357660b245c4491297d24eebc28b4ac2c21f -- 2.30.2