From dd9991dad0cbdc2f7ad2152fef927c2e1968c62b Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 11 Sep 2020 21:40:54 +0100 Subject: [PATCH] arch-arm: Fix ArmISA namespace requirement for Arm KVM This is needed after: https://gem5-review.googlesource.com/c/public/gem5/+/34155 Signed-off-by: Giacomo Travaglini Change-Id: I614b908a48145d8c2f5e8b8177448e3269f8dac9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34418 Reviewed-by: Gabe Black Tested-by: kokoro --- src/arch/arm/kvm/arm_cpu.hh | 4 ++-- src/arch/arm/kvm/armv8_cpu.cc | 2 ++ src/arch/arm/kvm/armv8_cpu.hh | 12 ++++++------ src/arch/arm/kvm/base_cpu.cc | 2 ++ 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/kvm/arm_cpu.hh b/src/arch/arm/kvm/arm_cpu.hh index 28453d7bd..cc3c93546 100644 --- a/src/arch/arm/kvm/arm_cpu.hh +++ b/src/arch/arm/kvm/arm_cpu.hh @@ -71,7 +71,7 @@ class ArmKvmCPU : public BaseKvmCPU /** KVM ID */ const uint64_t id; /** gem5 index */ - const IntRegIndex idx; + const ArmISA::IntRegIndex idx; /** Name in debug output */ const char *name; }; @@ -80,7 +80,7 @@ class ArmKvmCPU : public BaseKvmCPU /** KVM ID */ const uint64_t id; /** gem5 index */ - const MiscRegIndex idx; + const ArmISA::MiscRegIndex idx; /** Name in debug output */ const char *name; }; diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index b8ada8da2..1001f81d3 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -42,6 +42,8 @@ #include "debug/KvmContext.hh" #include "params/ArmV8KvmCPU.hh" +using namespace ArmISA; + // Unlike gem5, kvm doesn't count the SP as a normal integer register, // which means we only have 31 normal integer registers. constexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1; diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh index 987051051..dae9fe70c 100644 --- a/src/arch/arm/kvm/armv8_cpu.hh +++ b/src/arch/arm/kvm/armv8_cpu.hh @@ -93,27 +93,27 @@ class ArmV8KvmCPU : public BaseArmKvmCPU protected: /** Mapping between integer registers in gem5 and KVM */ struct IntRegInfo { - IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name) + IntRegInfo(uint64_t _kvm, ArmISA::IntRegIndex _idx, const char *_name) : kvm(_kvm), idx(_idx), name(_name) {} /** Register index in KVM */ uint64_t kvm; /** Register index in gem5 */ - IntRegIndex idx; + ArmISA::IntRegIndex idx; /** Name to use in debug dumps */ const char *name; }; /** Mapping between misc registers in gem5 and registers in KVM */ struct MiscRegInfo { - MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name, - bool _is_device = false) + MiscRegInfo(uint64_t _kvm, ArmISA::MiscRegIndex _idx, + const char *_name, bool _is_device = false) : kvm(_kvm), idx(_idx), name(_name), is_device(_is_device) {} /** Register index in KVM */ uint64_t kvm; /** Register index in gem5 */ - MiscRegIndex idx; + ArmISA::MiscRegIndex idx; /** Name to use in debug dumps */ const char *name; /** is device register? (needs 'effectful' state update) */ @@ -137,7 +137,7 @@ class ArmV8KvmCPU : public BaseArmKvmCPU /** Mapping between gem5 misc registers and registers in kvm */ static const std::vector miscRegMap; /** Device registers (needing "effectful" MiscReg writes) */ - static const std::set deviceRegSet; + static const std::set deviceRegSet; /** Mapping between gem5 ID misc registers and registers in kvm */ static const std::vector miscRegIdMap; diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc index 04c5d0fd0..6fd2651c6 100644 --- a/src/arch/arm/kvm/base_cpu.cc +++ b/src/arch/arm/kvm/base_cpu.cc @@ -45,6 +45,8 @@ #include "params/BaseArmKvmCPU.hh" #include "params/GenericTimer.hh" +using namespace ArmISA; + #define INTERRUPT_ID(type, vcpu, irq) ( \ ((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \ ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \ -- 2.30.2